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PRELIMINARY
AM79C850
SUPERNET(R) 3
DISTINCTIVE CHARACTERISTICS
s Compliant with the ANSI X3T9.5/ISO 9314
Advanced Micro Devices
s ANSI-compliant TP-PMD Stream Cipher
specification -- 100 Mbps data rate -- Timed token-passing protocol -- Ring topology s Complete memory management -- Supports 256K bytes of local frame buffer memory -- Supports buffer memory bandwidths of 200 Mbps and 400 Mbps -- Tag-Mode: minimum latency/highest performance buffer memory management, ideal for adapter card designs
Scrambling/Descrambling
s Full duplex operation: 200 Mbps continuous
data rate
s Supports both fiber optic and copper twisted-
pair media
s Diagnostic features
-- Built in Self Test (BIST) in Address Filter, Physical Layer Controller with Scrambler s Hardware Physical Connection Management support
s Low power consumption--reduction of more
than 25% from SUPERNET 2 solution
FUNCTIONAL OVERVIEW
SUPERNET 3 is a 208-pin CMOS integration of FDDI MAC, PHY, Address Filter, and clock generation and recovery functions. It is the third generation FDDI offering from AMD which integrates the SUPERNET 2 family of chips into a single-chip solution. Refer to the SUPERNET 2 data book (PID 15502C) for basic feature descriptions. The SUPERNET 3 is backward compatible to the SUPERNET 2 Tag Mode of operation in which the SUPERNET 3 buffer memory interface logic maintains the buffer memory as multiple FIFOs. The SUPERNET 3 provides DMA channels, arbitrates access to the network buffer memory, and controls the data path between the buffer memory and the medium. The MAC also implements the timed-token protocol and receive/transmit control as specified for the Media Access Control (MAC) sublayer of the ISO standard 9314-2 for FDDI. The Physical Layer functions defined by the ISO 9314-1 are performed by the SUPERNET 3. SUPERNET 3 implements on-chip digital clock recovery and transmit functions for fiber. To support copper media, the PHY-PMD interface is maintained and an external module can be implemented in the same footprint as the fiber optic transceiver to perform the MLT-3 encoding/decoding and equalization. SUPERNET 3 integrates the scrambler and descrambler functions for transmissions over copper media.
SUPERNET 3 FEATURES UPDATE
The basic feature description for SUPERNET 3 is provided in the SUPERNET 2 data book. The enhanced features are as listed below:
s This is a CMOS integration of the redesigned
FORMAC Plus, an enhanced PLC, a 32-entry address filter (AF, which is based on a Content Addressable Memory, or CAM, core), and a CMOS PDX core for clock and data recovery.
s A 32-entry, extensible and fully maskable AF
allows additional individual and group addresses to be supported.
s The physical data transmitter and receiver (PDX)
circuits are also embedded on-chip using proprietary digital clock-recovery technology.
s For the purposes of implementing copper PMD,
the scrambler/descrambler functions are embedded within the chip.
s The Buffer Memory interface has been modified to
support slower SRAM's (35 ns) without affecting backward compatibility with SUPERNET 2.
s SUPERNET 3 supports the FDDI single
attachment station (SAS) but is capable of supporting a dual attachment station (DAS)
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 19574 Rev. A Issue Date: April 1995
Amendment /0
AMD
PRELIMINARY
s All SUPERNET 3 registers will be initialized with a
configurations with an external physical layer controller.
s SUPERNET 3 has a Test Access Port and
default value on reset.
s The A, C indicator setting has been modified. It is
Boundary Scan Architecture, IEEE1149.1.
s SUPERNET 3 provides Built-in Self Test (BIST)
features for the Address Filter, and PLC-S.
s All registers are readable and writable by the Node
now possible to control the setting of the A, C indicators independent of the mode of operation (online, online special mode, and external loopback mode).
s Maskable `vectored-interrupts' are provided. It is
Processor. All reserved bits shall be read back as zero except where noted.
s The Receive Status (RS) pins are expanded from
5 to 6 pins to support enhanced status reporting.
s The Transmit Status (XS) pins are expanded from
now possible to detect the event causing the interrupt in the SUPERNET 3 in two cycles by reading the vector register which gives the vector of the status register followed by a read of the appropriate status register.
s An additional mode register (MDREG3) is
3 to 4 pins to support enhanced status reporting.
s Enhanced frame reception is possible by splitting
the receive queue.
s Modified TAG Mode of operation for easy
provided. Setting the bits in this mode register enables the additional SUPERNET 3 features.
conversion from NON-TAG SUPERNET 2 to SUPERNET 3.
2
SUPERNET 3
NPDATA NPADDR NPMODE 4 16 8 CS READY LSCLK BMCLK
BLOCK DIAGRAM
DS R/W
MINTR
RST
BCLK
Node Processor Interface Clock Logic
RBUS 10 10 3 TBUS 10 10 3 16 32 4 TX RX
XPAR
NPMEMREQ NPMEMACK
DAS/SAS Control & Mux
8 2 8 2
X XCU, XCL R RCU, RCL 3 RPAR LSR ULSB EBFERR FOTOFF ENCOFF
HSREQ HSACK RDATA1 QCTRL
Enhanced F+
NPCONTROL
RDAT 5
PRELIMINARY
TDI
TDO
TCK
TMS
XSAMAT
XDAMAT
RXAFCL RXAFCU
XSA_XACT
XDA_XACT
RXAFL[3:0]
RXAFU[3:0]
4
TRST
SUPERNET 3
2
NPDATA
ADDR BD BDP BDTAG CSO RD, WR 6 16
NPADDR
Enhanced PLC with Scrambler Descrambler
FLXI RS XS 6 4 8
Digital 5 Xmitter/ Receiver TDAT (PDX)
LPBCK
TX+ TXRX+ RXSDI+ SDISCRM
RDATA2
RXINT 8 CONTROL MATCH STATUS 8 4
Address Filter
Tap Controller
4
AMD
3
AMD
PRELIMINARY
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUPERNET 3 Features Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 3 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SUPERNET 2 Features not Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Miscellaneous Changes from SUPERNET 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Explanation of Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Slower Buffer Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 A, C Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Non-Tag Mode of Operation No Longer Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Modified TAG Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transmit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TDAT Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mode Register 3 (MDREG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Flush/Transmit Inhibit pin FLXI (input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Single Frame Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Receive Queue Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Address Bit Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Auto-Unlocking of Receive Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Symbol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dual Attachment Station (DAS) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes and Enhancements to PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Summary of Changes to Status and Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Status Register 3 (ST3U & ST3L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Parity Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Node Processor Synchronous Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Address Filter (AF) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Function of the Address Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Node Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4
SUPERNET 3
PRELIMINARY
AMD
Table of Contents (continued)
Address Filter Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test Logic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Writing Entries into the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Finding Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Invalidating Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PDX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Default Timer and Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SUPERNET 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SUPERNET 3 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SUPERNET 3 Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SUPERNET 3 Command Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SUPERNET 3 Command Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Revision I.D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DC CHARACTERISTICS over operating ranges unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PQR208, Trimmed and Formed 208-Pin Plastic Quad Flat Pack (measured in inches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SUPERNET 3
5
AMD
PRELIMINARY
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Memory Receive Queue (Modified TAG Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register 3 (MDREG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Selection Register (FRSELREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay Register (UNLCKDLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THRU_A Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRAP_A Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRAP_B Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRAP_S or SAS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 1 - Upper 16 Bits (ST1U) (NPADDR = 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 1 - Lower 16 Bits (ST1L) (NPADDR = 01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 2 - Upper 16 Bits (ST2U) (NPADDR = 02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 2 - Lower 16 Bits (ST2L) (NPADDR = 03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 1 (MDREG1) (NPADDR = 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 2 (MDREG2) (NPADDR = 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 3 - Upper 16 Bits (ST3U) (NPADDR = 61h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register 3 - Lower 16 Bits (ST3L) (NPADDR = 62h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Memory Queue Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Processor Comparand Register (AFCOMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Processor Comparand Register (AFCOMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Processor Comparand Register (AFCOMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Register (AFMASK2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Register (AFMASK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Register (AFMASK0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Personality Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AF-MAC Interface Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NP Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NP Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NP Synchronous Read and Write Except MDR Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NP Synchronous Read and Write MDR Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NP DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Memory Read Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Memory Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC Miscellaneous Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External CAM Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Miscellaneous Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST Interface Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMD Interface Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 26 29 31 32 32 33 33 41 41 42 42 43 43 44 45 47 50 52 54 54 55 56 56 57 58 60 78 80 81 82 83 84 85 87 88 88 89 90 91 92 93 94
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CONNECTION DIAGRAM
208-Pin PQR (Top View)
VSSO ADDR[15] ADDR[14] ADDR[13] ADDR[12] VSSO ADDR[11] ADDR[10] ADDR[9] ADDR[8] VCCO ADDR[7] ADDR[6] ADDR[5] ADDR[4] VSSO ADDR[3] ADDR[2] ADDR[1] ADDR[0] VSSO QCTRL[0] QCTRL[1] QCTRL[2] VCC HSACK HSREQ[0] HSREQ[1] HSREQ[2] RDATA1 RDATA2 VCCO BD[0] BD[1] BD[2] BD[3] VSSO BD[4] BD[5] BD[6] BD[7] VSSO BD[8] BD[9] BD[10] BD[11] BD[12] BD[13] BD[14] BD[15] RD VCCO
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180
179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VSSP SCRM ENCOFF EBFERR VSSD VCCD TX+ TXVCCE VSSE RXRX+ SDISDI+ FOTOFF ULSB LSR[2] LSR[1] LSR[0] RPAR R[0] R[1] R[2] VSS R[3] R[4] R[5] R[6] R[7] RCL RCU FLXI VSSO XPAR X[0] X[1] X[2] X[3] X[4] X[5] X[6] X[7] XCL SCU VSS XS[0] XS[1] XS[2] XS[3] RS[0] RS[1] VCCO
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
VSSO NP[15] NP[14] NP[13] NP[12] NP[11] NP[10] VCCO NP[9] NP[8] NP[7] VSSO NP[6] NP[5] NP[4] NP[3] NP[2] NP[1] NP[0] VSSO MINTR1 MINTR2 MINTR3 MINTR4 BMCLK VSS BCLK VCC NPMEMRQ NPMEMACK VSS READY R/W DS CSI LSCLK NPA[7] NPA[6] NPA[5] NPA[4] NPA[3] NPA[2] NPA[1] NPA[0] NPMODE RST TRST TCK TMS TDI TDO VCCP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VSSO WR CSO BD[16] BD[17] BD[18] BD[19] VCCO BD[20] BD[21] BD[22] BD[23] VSSO BD[24] BD[25] VSS BD[26] BD[27] BD[28] VCC BD[29] BD[30] BD[31] BDP[3] VSSO BDP[2] BDP[1] BDP[0] BDTAG VSSO RXAFL[0] RXAFL[1] RXAFL[2] RXAFL[3] RXAFU[0] RXAFU[1] RXAFU[2] VSS RXAFU[3] RXAFCL RXAFCU VCC XDAMAT XDA_XACT XSAMAT XSA_XACT VCC RS[5] RS[4] RS[3] RS[2] VCCO
19574A-1
SUPERNET 3
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PQFP PIN DESIGNATIONS Listed by Pin Number
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Description VSSO NP[15] NP[14] NP[13] NP[12] NP[11] NP[10] VCCO NP[9] NP[8] NP[7] VSSO NP[6] NP[5] NP[4] NP[3] NP[2] NP[1] NP[0] VSSO MINTR1 MINTR2 MINTR3 MINTR4 BMCLK VSS BCLK VCC NPMEMRQ NPMEMACK VSS READY R/W DS Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Description CSI LSCLK NPA[7] NPA[6] NPA[5] NPA[4] NPA[3] NPA[2] NPA[1] NPA[0] NPMODE RST TRST TCK TMS TDI TDO VCCP VSSP SCRM ENCOFF EBFERR VSSD VCCD TX+ TX- VCCE VSSE RX- RX+ SDI- SDI+ FOTOFF ULSB Pin # 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Description LSR[2] LSR[1] LSR[0] RPAR R[0] R[1] R[2] VSS R[3] R[4] R[5] R[6] R[7] RCL RCU FLXI VSSO XPAR X[0] X[1] X[2] X[3] X[4] X[5] X[6] X[7] XCL XCU VSS XS[0] XS[1] XS[2] XS[3] RS[0] Pin # 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Description RS[1] VCCO VCCO RS[2] RS[3] RS[4] RS[5] VCC XSA_XACT XSAMAT XDA_XACT XDAMAT VCC RXAFCU RXAFCL RXAFU[3] VSS RXAFU[2] RXAFU[1] RXAFU[0] RXAFL[3] RXAFL[2] RXAFL[1] RXAFL[0] VSSO BDTAG BDP[0] BDP[1] BDP[2] VSSO BDP[3] BD[31] BD[30] BD[29]
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PQFP PIN DESIGNATIONS Listed by Pin Number
Pin # 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 Description VCC BD[28] BD[27] BD[26] VSS BD[25] BD[24] VSSO BD[23] BD[22] BD[21] BD[20] VCCO BD[19] BD[18] BD[17] BD[16] CSO Pin # 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Description WR VSSO VCCO RD BD[15] BD[14] BD[13] BD[12] BD[11] BD[10] BD[9] BD[8] VSSO BD[7] BD[6] BD[5] BD[4] VSSO Pin # 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Description BD[3] BD[2] BD[1] BD[0] VCCO RDATA2 RDATA1 HSREQ[2] HSREQ[1] HSREQ[0] HSACK VCC QCTRL[2] QCTRL[1] QCTRL[0] VSSO ADDR[0] ADDR[1] Pin # 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Description ADDR[2] ADDR[3] VSSO ADDR[4] ADDR[5] ADDR[6] ADDR[7] VCCO ADDR[8] ADDR[9] ADDR[10] ADDR[11] VSSO ADDR[12] ADDR[13] ADDR[14] ADDR[15] VSSO
SUPERNET 3
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AMD
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of:
AM79C850
K
C
\W
ALTERNATE PACKAGING OPTION \W = Trimmed and Formed in a Tray (PQJ208) OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C)
PACKAGE TYPE K = Plastic Quad Flat Pack in TapePak (PQR208)
SPEED OPTION Not Applicable
DEVICE NUMBER/DESCRIPTION AM79C850 SUPERNET 3
Valid Combinations AM79C850 KC, KC\W
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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SUPERNET 3
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AMD
PIN DESCRIPTION
I/O pins can only be high impedance in Test Access Port (TAP) operation. Refer to TAP Testability section.
RXAFL3-0
Receive Bus Tap for External AF (TTL output, TTL input, high impedance) The internal MAC Receive bus lines lower nibble are tapped and brought out as the RXAFL 3-0 pins. These pins are used by an external AF to do external SA and/or DA match.
PHY/PMD Interface (46 Pins) RX+, RXReceive Data (PECL Input) These pins receive differential NRZI data.
TX+, TXTransmit Data (PECL Output) These transmit outputs carry differential NRZI data. They can be forced to logical 0 (TX+ LOW, TX- HIGH) by asserting the FOTOFF input.
Note: The RXAFL[3:0] input pins are for diagnostic purposes only.
RXAFCU
Control Upper for AF Receive Bus (TTL output, high impedance) The RXAFCU output signal is used to flag control symbols being presented on the nibble (3:0) of the RXAFU bus. This signal is synchronous to BCLK. If RXAFCU is asserted high, the nibble on the RXAFU bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble.
RCU
Receive Control Upper (TTL input) RCU is asserted high to indicate that the upper nibble of the R bus (R7-4) is a network control character. When RCU is low, this nibble contains data. RCU is synchronous to BCLK. This pin has internal pull-up.
RXAFCL
Control Lower for AF Receive Bus (TTL output, TTL input, high impedance) The RXAFCL output signal is used to flag control symbols being presented on the nibble (3:0) of the RXAFL bus. This signal is synchronous to BCLK. If RXAFCL is asserted high, the nibble on the RXAFL bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble.
RCL
Receive Control Lower (TTL input) RCL is asserted high to indicate that the lower nibble of the R bus (R3-0) is a network control character. When RCL is low, this nibble contains data. RCL is synchronous to BCLK. This pin has internal pull-up.
R7-0
Receive Bus (TTL input) The R bus is used to receive information from the external physical layer (PHY) device. Bytes clocked from the physical layer (PHY) into the SUPERNET 3 R-bus input are synchronous to the BCLK. These pins have internal pull-up.
Note: The RXAFCL purposes only.
input
is
for
diagnostic
X7-0
Transmit Bus (TTL output, high impedance) This eight-bit output bus is used to send control and data information to the external physical layer (PHY) device to be transmitted over the medium. Information on the X-bus output is synchronous to the BCLK.
RPAR
Receive parity (TTL input) RPAR is an input signal used to enhance error detection on the external PHY interface R7:0 bus. RPAR is an input signal used to implement even parity checking on R bus. If there is an odd number of 1's on {R7:0, RCU, RCL}, then RPAR should be 1 and if there is an even number of 1's on {R7:0, RCU, RCL} then RPAR should be 0. This pin has internal pull-up.
XPAR
Transmit parity (TTL output, high impedance) XPAR is an output signal used to enhance error detection on the MAC--external PHY interface X7:0 bus. If there is an odd number of 1's on {X7:0, XCU, XCL}, then XPAR should be 1 and if there is an even number of 1's on {X7:0, XCU, XCL} then XPAR should be 0.
RXAFU3-0
Receive Bus Tap for External AF (TTL output, high impedance) The internal MAC Receive bus lines upper nibble are tapped and brought out as the RXAFU 3-0 pins. These pins are used by an external AF to do external SA and/or DA match.
XCU
Transmit Control Upper (TTL output, high impedance) The XCU output signal is used to flag control symbols being presented on the upper nibble of the transmit bus. This signal is synchronous to BCLK. If XCU is asserted
SUPERNET 3
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high, the upper nibble of the X-bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble.
EBFERR
Elasticity Buffer Error (TTL Output, Active High, high impedance) EBFERR indicates when an overflow or underflow condition occurs in the Elasticity Buffer.
XCL
Transmit Control Lower (TTL output, high impedance) The XCL output signal is used to flag control symbols being presented on the lower nibble of the transmit bus. This signal is synchronous to BCLK. If XCL is asserted high, the lower nibble of the X-bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble.
ENCOFF
Encoder Off (TTL Input, Active High) ENCOFF signal turns off the 4B/5B encoding and decoding function of the PLC core.
ULSB
Unknown Line State (TTL Output, high impedance) The ULSB signal directly outputs the UNKN_LINE_ST bit of the PLC_STATUS_A register to ring test and monitor equipment.
FOTOFF
Fiber Optic Transmitter Off (TTL Output, Active Low, high impedance) The FOTOFF signal, when asserted, causes the optical transmitter to turn off.
Clock Pins (3 Pins) LSCLK
Local Symbol Clock pin (TTL input) The LSCLK is a 25 MHz clock. It is used by the PLC core.
SDI+, SDISignal Detect (PECL Differential Line Receiver Inputs) The SDI input signal pair is from the optical or copper transceivers to indicate whether the received optical or electrical signal is above its threshold. The inverted value of this signal is held in the PHY_STATUS_A register, and the LSDO interrupt bit in the PHY is set whenever SDI becomes asserted.
BCLK
Byte Clock pin (TTL input) The BCLK is a 12.5 MHz clock. It is used by the PLC and the MAC cores.
BMCLK
Buffer Memory Clock pin (TTL input) The BMCLK is the clock signal that the MAC core uses for generating the signals to the buffer memory. BMCLK is driven with either a 12.5 or 25 MHz clock signal. If 12.5 MHz operation is desired, then this pin can be tied to BCLK pin. If 25 MHz operation is desired, then this pin can be tied to LSCLK pin.
SCRM
Scrambler/Descrambler enable (DC Input, Active High) When this pin is strapped high, the SUPERNET 3 is set to operate with a copper PMD and the scrambler/ descrambler is enabled. When the pin is strapped to ground, then the scrambler/descrambler function is disabled in the SUPERNET 3, and the SUPERNET 3 is set to operate with a fiber PMD. This pin is ORed with the bit 0 (CIPHER_ENABLE) in the PLC_CNTRL_C register and the result is indicated in the same bit (bit 0). The PMD selection and scrambler/descrambler (S/D) enabling is as follows:
SCRM pin Low Low High High CIPHER_ ENABLE bit Reset Set Reset Set
Node Processor (NP) Interface (35 Pins)
The following paragraphs describe the pins used to interface the SUPERNET 3 with the node processor (NP) or other control devices. The NP interface is used for initializing the SUPERNET 3 as well as for reporting status.
Result Fiber PMD. S/D disabled. Copper PMD. S/D enabled. Copper PMD. S/D enabled. Copper PMD. S/D enabled.
CSI
Chip Select Input (TTL input, active low) - Asynchronous when NPMODE = 0 - Synchronous when NPMODE = 1 The Chip Select Input (active low) enables Read and Write operations to the SUPERNET 3. In the asynchronous mode, the data output is enabled while CSI and DS are both low and R/W is high. In the synchronous mode, the data output is enabled while CSI is low and R/W is high.
LSR 2-0
Line State Register (TTL Output, high impedance) The LSR2-0 signals directly output the LINE_ST field of the PLC_STATUS_A register to ring test and monitor equipment.
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DS
Data Strobe/ (TTL input, active low) - Asynchronous when NPMODE = 0 - Synchronous when NPMODE = 1 The DS input (active low) is used in the handshake between the NP and SUPERNET 3 when the SUPERNET 3 acts as bus slave during register accesses. In the asynchronous mode, this input signal is set by the node processor to transfer data between the NP and the SUPERNET 3. The direction of the data transfer is dictated by the logic level of the R/W line. The NP sets DS low to initiate a data transfer. DS is not used in the synchronous mode. The chip-select input (CSI) must be low while DS is low in order to start an NP bus transaction.
READY
Ready (TTL output, open drain, active low, high impedance) In asynchronous mode, the READY output (active low) is used in the handshake between the NP and SUPERNET 3. The SUPERNET 3 READY output provides an asynchronous acknowledgment to the NP that data transfer is complete. The SUPERNET 3 asserts READY when it has put the data onto the NP bus during a read cycle, or when it has taken the data from the NP bus during a write cycle. READY is a response to the CSI and DS inputs, and returns high after the CSI or DS signals go high. In the synchronous mode, the READY line goes active on the BCLK edge when CSI and DS are active. READY goes inactive on the following BCLK edge. In the case of loading/reading of the MDR (memory data register), READY goes active on the BCLK edge after the completion of any pending data transfer from/to buffer memory.
NPADDR7-0
NP Address Bus (TTL input) The NPADDR7-0 input lines allow direct access to SUPERNET 3 internal registers. In addition, these lines are used to place SUPERNET 3 into different operating states. The NPADDR bus of the SUPERNET 3 performs two control functions. First, the input on NPADDR7-0 acts as an address, selecting the proper internal register for a read or write operation that is controlled by the R/W pin. The data is either read onto or loaded from the 16-bit NP bus. For a discussion of the results of read and load instructions, see the section under Programming the FORMAC Plus in the SUPERNET 2 data book. Second, instructions or commands can be issued to SUPERNET 3 by using the NPADDR bus.
R/W
Read/Write Select (TTL input) The R/W line is used to select the type of access (i.e., read or write) between the SUPERNET 3 and the NP. If R/W is high, data is read from the SUPERNET 3 to the NP. If R/W is low, the data flow is from the NP to the SUPERNET 3.
MINTR1
Maskable Interrupt 1 (TTL output, open drain, high impedance) The MINTR1 output (active low) is an attention line to the NP. MINTR1, when active, indicates an interrupt due to one or more unmasked flags in status register 1. In general, the active state of MINTR1 indicates that an unmasked interrupt condition or a transmit condition has occurred. MINTR1 is deactivated once either the lower or upper 16 bits of status register 1 (ST1L or ST1U) are read. Once MINTR1 is asserted, all 32 bits of status register 1 must be read to enable any future interrupt on this pin.
NPDATA15-0
NP Data Bus (TTL input, TTL output, high impedance) The NP data bus is a 16-bit wide bidirectional data bus used to interface the SUPERNET 3 to the node processor. Data transfer on the NP data bus can be synchronous or asynchronous depending upon the setting of the NPMODE pin. For asynchronous operation, a two-wire handshake is provided through the READY and data-strobe (DS) lines.
MINTR2
Maskable Interrupt 2 (TTL output, open drain, high impedance) The MINTR2 output (active low) is an attention line to the NP. MINTR2, when active, indicates an interrupt due to one or more unmasked flags in status register 2. In general, the active state of MINTR2 indicates that an unmasked interrupt condition, a receive condition, or a
NPMODE
NP Bus Mode (TTL input) The level on the NPMODE pin defines the type of NP-bus interface with the SUPERNET 3. When NPMODE is strapped high, the NP interface operates synchronously with BCLK. When NPMODE is strapped low, asynchronous interface operation is selected.
SUPERNET 3
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AMD
PRELIMINARY
change in ring status has occurred. MINTR2 is deactivated once either the lower or upper 16 bits of status register 2 (ST2L or ST2U) are read. Once MINTR2 is asserted, all 32 bits of status register 2 must be read in order to enable any future interrupt on this pin.
SUPERNET 3/Buffer Memory Interface (56 Pins) ADDR15-0
Buffer Memory Address (TTL output, high impedance) The 16-bit ADDR-bus provides the addresses that access the buffer memory. The address selection depends on the result of bus arbitration in the SUPERNET 3. Each memory access lasts for two BMCLK clock cycles and the address is valid for both of these cycles. When buffer memory control has been released to the NP, the ADDR bus is in the high-impedance state.
MINTR3
Maskable Interrupt 3 (TTL output, open drain, high impedance) The MINTR3 output (active low) is an attention line to the NP. MINTR3, when active, indicates an interrupt due to one or more unmasked flags in status register 3. In general, the active state of MINTR3 indicates that an unmasked interrupt condition, a receive condition in the second receive queue has occurred. MINTR3 is deactivated once either the lower or upper 16 bits of status register 3 (ST3L or ST3U) are read. Once MINTR3 is asserted, all 32 bits of status register 3 must be read in order to enable any future interrupt on this pin.
MINTR4
Maskable Interrupt 4 (TTL output, open drain, high impedance) The MINTR4 output (active low) is an attention line to the NP. MINTR4, when active, indicates an interrupt due to one or more unmasked flags in the PHY interrupt event (INTR_EVENT) register. In general, the active state of MINTR4 indicates that a change in PCM state machine or timer expiration or counter overflow has occurred. MINTR4 remains active until cleared by reading the INTR_EVENT register. When the MENSNGLINT (MDREG 3, bit 10) is set, the SUPERNET 3 generates only one interrupt (MINTR4) and the other interrupt lines (MINTR1, MINTR2, and MINTR3) are not toggled. The SUPERNET 3 operates in a vectored interrupt mode, i.e., a vector register is read to determine which status register is the source of the interrupt.
Note: As long as the use of the buffer memory has not been granted to the node processor or host (HSACK and NPMEMACK not active), the SUPERNET 3 may drive the address lines even though no control signals are active.
BD31-0
Buffer Memory Data Bus (TTL input, output, high impedance) The 32-bit BD bus interfaces the SUPERNET 3 to the buffer memory or any external logic using this bus. These lines transfer data to and from the buffer memory for the SUPERNET 3. These signals are synchronous to BMCLK.
BDP3-0
Buffer Data Parity Bus (TTL input, output, high impedance) The BDP3-0 bus contains the four byte-parity lines for the BD bus as shown in the following table:
BD-Bus Lines BD7-0 and tag bit BD15-8 BD23-16 BD31-24 Corresponding Parity Lines BDP0 BDP1 BDP2 BDP3
NPMEMRQ
Node Processor Memory Request (TTL input) The input signal NPMEMRQ is a request by the node processor to obtain control of buffer memory.
NPMEMACK
Node Processor Memory Access Acknowledge (TTL output, high impedance) This signal indicates that an NPMEMRQ has been granted and that the NP now has control of buffer memory (ADDR-bus, RD, WR, CSO, BDP, BD, and BDTAG). If NPMEMACK is forced low while NPMEMRQ is active (due to a higher priority request), the NP must release control of the bus within two BMCLK periods after the NPMEMACK line goes inactive.
Note: BD bus parity can be either even or odd, based on the state of the parity bit (bit 12) in mode register 2 (MDREG2).
BDTAG
Buffer Data Tag Indication (TTL input, output, high impedance) In receive mode, this bit defines whether the information on the BD bus is data (BDTAG = 0) or frame status (BDTAG = 1). In transmit mode, when BDTAG = 1, it indicates that the end of a frame has been reached, as indicated by the presence of a tag bit in both the last long
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SUPERNET 3
PRELIMINARY word and the descriptor word at the end of the frame. In transmit mode, when BDTAG = 0, it indicates that the information on the BD bus is data, i.e., end-of-frame not yet reached.
HSREQ2 0 0 HSREQ1 0 0 HSREQ0 0 1
AMD
Type of Request None. Read Request: Second Receive Queue* Special Frame Write Request. Read Request: Receive Queue. Write Request: Synchronous Queue. Write Request: Asynchronous Queue 0. Write Request: Asynchronous Queue 1. Write Request Asynchronous Queue 1.
CSO
Chip-Select Output (TTL output, high impedance, active low) The chip-select output (active low) is a select signal for buffer memory read and write operations. This line is in the high-impedance state when buffer memory control is released to the NP.
0 0 1 1 1 1 0 0 0 1 0 1
RD
Buffer Memory Read (TTL output, high impedance, active low) This output signal (active low) controls the buffer memory during a buffer-memory read accesses. This line is in the high-impedance state when buffer memory control is released to the NP.
1
1
0
WR
Buffer Memory Write (TTL output, high impedance, active low) This (active low) output signal, in its active-low state, allows write accesses to buffer memory. This line is in the high-impedance state when buffer memory control is released to the NP.
1
1
1
Note: * Only if two receive queue operation is selected through MDREG3.
QCTRL2-0
Buffer Queue Control (TTL output, high impedance) The QCTRL2-0 status output lines are encoded as described in the following table.
Host/Buffer Memory Interface (10 Pins)
All these signals are synchronous to BMCLK.
HSACK
Host Acknowledge (TTL output, high impedance) This signal indicates that the current host read/write request is being granted by SUPERNET 3 and allows read/write accesses of buffer memory by the host.
HSREQ2-0
Host Request Bus (TTL input) The host request bus specifies to SUPERNET 3 the type of buffer memory access the host requires, as described in the following table. Special-frame write requests are used to set up claim, beacon, and auto-void frames in the buffer memory (see the discussion under Buffer Memory Operation in SUPERNET 2 data book). These requests make use of the WPXSF register to set up special frames in the special-frame area. Read request is used to retrieve received frames from buffer memory and store them in the system memory. Write requests are used to set up frames in buffer memory for transmission.
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QCTRL2 0 QCTRL1 0 QCTRL0 0
PRELIMINARY
Indicated Status (1) Quiescent. (2) Space remains for more data while loading a transmit queue Unloading transmit frame from Synchronous Queue Unloading transmit frame from Asynchronous Queue 0 Unloading transmit frame from Asynchronous Queue 1 Reserved Current transmit frame Underrun Current transmit queue full. Current transmit queue almost full
this state does not exist in SUPERNET 2, it is added in SUPERNET 3.
E. QCTRL[2:0] = 111
This state means the number of free long words remaining in the transmit queue which the current write request is for has decreased to the almost-full value (AFULL3-0) programmed in mode register 2. This signal condition is asserted for one BMCLK cycle only as in the FORMAC PLUS if the MENAFULL bit in the mode register 3 is not set. If this bit is set, this state will remain for every cycle as long as the queue is in almost full condition and it is not yet full.
0
0
1
0
1
0
0
1
1
Note: If AFULL3-0 is set to 000, this state is not presented, even when the transmit FIFO in buffer memory is full.
1 1 1 1
0 0 1 1
0 1 0 1
RDATA1
Receive Data for Receive Queue #1 (TTL output, high impedance) This signal indicates that received data is present in the buffer memory and is ready to be transferred by the host to system memory. Read requests are not acknowledged when RDATA1 is inactive.
These signals communicate to the host the current condition of the transmit queues. This provides useful information for doing the host interface. The meaning of these states are as follows:
RDATA2
Receive Data for Receive Queue #2 (TTL output, high impedance) This signal indicates that received data is present in the buffer memory and is ready to be transferred by the host to system memory. Read requests are not acknowledged when RDATA2 is inactive.
A. QCTRL[2:0] = 000
The quiescent state exists when SUPERNET 3 is neither transmitting nor receiving. This state is also true while loading a transmit queue (making a write request to a queue) and not yet unloading it, and when there is space in the queue for more data.
B. QCTRL[2:0] = 001, 010 or 011
These states indicate unloading frame from the Synchronous Queue, Asynchronous Queue 0 or Asynchronous Queue 1, respectively. They are valid as long as the corresponding queue is not yet in the almost full or full state and, at the same time, the SUPERNET 3 is reading out of the queue. The host can transfer more data into the corresponding queue when any of these states is present. These three combinations may appear one BMCLK period later than the time indicated in the timing diagram.
Special Functions and Control Pins (16 Pins) FLXI
Flush/Inhibit (TTL input) The SUPERNET 3 FLXI pin can be programmed to perform either of two functions: it can provide a flush received frame function for the chip or it can provide an unconditional transmit-inhibit function. If the FLUSH function is selected and the pin is asserted by external logic, then the incoming frame is flushed. The buffer memory pointers are not advanced from where they were before the frame was received. This prevents unwanted frames and fragments from occupying receive buffer space and taking up the buffer memory bus bandwidth. If the TRANSMIT INHIBIT function is selected and the pin is asserted by external logic, then the SUPERNET 3 completes transmitting the current frame (if transmitting) releases the token and no further transmissions can occur until the pin is deasserted. During the time that the TRANSMIT INHIBIT function is enabled, the network timers and state machines operate normally.
C. QCTRL[2:0] = 101
This state is present when all of the following three conditions are satisfied: 1. The host has issued a write request for this queue 2. Transmit FIFO underrun occurs 3. Transmit buffer-memory underrun occurs for this queue
D. QCTRL[2:0] = 110
When the transmit queue being requested is full, this state is presented at the queue control signals. Note that 16
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RS5-0
Receive Status (TTL output, high impedance) The receive-status (RS4-0) pins indicate the type of frame received, and the condition of the receive state
RS5 0 1 1 1 1 1 1 1 1 RS4 X 0 0 0 0 0 0 0 0 RS3 X 0 X 0 0 0 0 0 0 RS2 X 0 0 0 0 1 1 1 1 through 1 1 1 1 1 RS1 X 0 0 1 1 0 0 1 1
machine. The RS4-0 status output pins are encoded as illustrated in Table 3 in the SUPERNET 2 data book and the enhancements RS5-0 are described here.
RS0 X 0 1 0 1 0 1 0 1
Indicated Status As in SUPERNET 2 FORMAC Plus Reserved Starting Delimiter and non-data symbol received OSM mode: Stripping frame Reserved Reserved Frame Abort Frame Flush Reserved
1
Reserved
XS3-0
Transmit Status (TTL output, high impedance) The transmit-status (XS3-0) pins indicate the transmit status conditions of the MAC and are valid for one clock cycle. These status signals are not present for repeated or stripped frames. These status output pins are encoded as illustrated in Table 4 (SUPERNET 2 data book) and the enhancements are described here.
XS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 XS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 XS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 XS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Indicated Status Quiescent. Transmit Aborted. Token Issued Reserved. Transmitting Synchronous Queue. Transmitting Asynchronous Queue 0. Transmitting Asynchronous Queue 1. Reserved Reserved Initiated Claim. Initiated Beacon. Initiated Void MAC Frame Aborted Void Frame Aborted
XDAMAT
External Destination Address Match (TTL input, active low) This input provides a means for additional destinationaddress detection external to the SUPERNET 3. This pin should be tied high when external destination-address detection is not used. This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a subsequent external destination address match is recognized. The XDAMAT pin which is generated by the external AF is logically ORed with the "af_da" output signal generated by the internal AF logic. This pin should be tied high when external address detection (such as an external AF) is not used.
XDA_XACT
External Destination Address Exact Match (TTL input, active low) This input indicates whether the external address match was exact (low) or inexact (high). This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a subsequent external source address match is recognized. It must be asserted and deasserted in an identical
SUPERNET 3
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PRELIMINARY The XSA_XACT pin which is generated by the external AF is logically ORed with the "af_sax" output signal generated by the internal AF logic. This pin is enabled only if the MENXACT bit in the mode register 3 is set. This pin should be tied high when external address detection (such as an external AF) is not used.
fashion to the XDAMAT pin. This input is used in conjunction with the XDAMAT pin as follows:
Match XDA_XACT and XDAMAT XDA_XACT and XDAMAT XDA_XACT and XDAMAT XDA_XACT and XDAMAT Action A, C indicators set and frame copied*. Invalid combination. Ignored by MAC. A, C indicators not set and frame copied. No action.
RST
Reset (TTL input) The RST signal (active low) is an asynchronous input that initializes the internal SUPERNET 3 state machines and registers. Once RST is asserted low, it must remain asserted for at least twenty BCLK cycles. When it is deasserted the SUPERNET 3 is ready to begin normal operation only after 750 LSCLK cycles. The 750 LSCLK cycles are needed for calibration of the PDX core. Assertion and deassertion are asynchronous. A warm reset (assertion of RST after the device is in operation) will cause device outputs to be unpredictable until the device is initialized.
* Frame is copied if valid frame or if in promiscuous or limited promiscuous mode. In OSM, the A, C indicators are set according to the OSM rules if bits 4, 5 (MEIND0,1) are set. The XDA_XACT pin which is generated by the external AF is logically ORed with the "af_dax" output signal generated by the internal AF logic. This pin is enabled only if the MENXACT bit in the mode register 3 is set. This pin should be tied high when external address detection (such as an external AF) is not used.
XSAMAT
External Source Address Match (TTL input, active low) This input provides a means for additional source-address detection external to the SUPERNET 3. This pin should be tied high when external source-address detection is not used. This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a subsequent external destination address match is recognized. The XSAMAT pin which is generated by the external AF is logically ORed with the "af_sa" output signal generated by the internal AF logic. This pin should be tied high when external address detection (such as an external AF) is not used.
Testability Interface (5 Pins) TCK
Test Clock In (TTL input) TCK provides the clock for the test logic. Any storedstate devices contained in the test logic must retain their state indefinitely if the signal applied to TCK is held high or low.
TMS
Test Mode Select In (TTL input, Synchronous to TCK) The test mode select input directs the operation of the generation of the TAP controller. The state of the TMS signal is sampled on the rising edge of TCK. If for some reason TMS is not driven externally, the TAP controller should behave as if this signal were driven with a logic 1 (internal pull-up).
XSA_XACT
External Source Address Exact Match (TTL input, active low) This input indicates whether the external source address match was exact (low) or inexact (high). This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a subsequent external source address match is recognized. It must be asserted and deasserted in an identical fashion to the XSAMAT pin. This input is used in conjunction with the XSAMAT pin as follows:
Match XSA_XACT and XSAMAT XSA_XACT and XSAMAT XSA_XACT and XSAMAT XSA_XACT and XSAMAT Action Frame stripped. Invalid combination. Ignored by MAC. Frame not stripped. No action.
TDI
Test Data In (TTL input, Synchronous to TCK) This pin provides for the application of serial instructions and data. The state of this signal is sampled on the rising edge of TCK. If for some reason TDI is not driven externally, the test logic should behave as if a logic 1 were applied to this signal (internal pull-up).
TDO
Test Data Output (TTL Output, 3-state, Synchronous to TCK) This pin provides the serial output for instructions and data from the test logic. No inversion of data is allowed between TDI and TDO during shift operations. The state of TDO changes on the falling edge of TCK. TDO is in the high impedance state except during shifting operations.
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TRST
Test Reset (asynchronous TTL input, active low) This input is provided for asynchronous initialization of the TAP controller. When a logic 0 is applied, the TAP controller must go to the Test-Logic-Reset state. If for some reason TRST is not driven externally, the test logic should behave as if a logic 1 were applied (internal pull-up). This pin can not be used to initialize any system logic.
is crossed until the queue is full while a Host write request is asserted. Currently, the signal is asserted for one clock only.
s `XDA_XACT' and `XSA_XACT' input signals are
provided for the external CAM (if implemented).
s For increased robustness, all internal tri-state
busses will have a driven default state and will not be allowed to float.
s The Node Processor access interface has been
Power and Ground (37 Pins) GND
Ground (input) There are 23 ground (GND) pins on the SUPERNET 3 chip. They must all be connected to a common external ground reference.
streamlined to two modes: 1) The FORMAC Plus asynchronous access mechanism for accessing all blocks. 2) The PLC two-cycle synchronous access mechanism for accessing all blocks. s There are four interrupt pins: two generated by the two MAC status registers, one generated by the AF and one generated by the PHY status register.
VCC
+5 V Power (input) There are 15 pins carrying +5-V power (VCC) on the SUPERNET 3 chip. They must all be connected to a 5 V 5% source.
EXPLANATION OF ENHANCEMENTS Status Pins XS 3:0
Transmit Status pins (outputs) An additional transmit status pin has been added to provide more transmit information. The encoding of the status pins is fully backward compatible with the SUPERNET 2 chipset. The enhanced encoding is enabled by setting the MENXS bit in the mode register 3 (MDREG3). The encoding of the XS pins is as follows:
XS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 XS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 XS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 XS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Indicated Status Quiescent Transmit Aborted Token Issued Reserved Transmitting Synchronous Queue Transmitting Asynchronous Queue 0 Transmitting Asynchronous Queue 1 Reserved Reserved Initiated Claim Initiated Beacon Initiated Void MAC Frame Aborted Void Frame Aborted Reserved Reserved
SUPERNET 2 Features not Supported
The following features are SUPERNET 3 in any mode. not supported in
s SUPERNET 3 supports the Tag Mode of operation
for the system-to-buffer-memory and network (MAC)-to-buffer-memory interfaces. Non-Tag mode of operation is no longer supported.
s SUPERNET 3 supports three transmit queues:
Synchronous, Async0 and Async1. Async2 is no longer supported.
s The `Disable Carry' (DISCRY) function is no
longer supported. Setting of the DISCRY bit in the mode register 1 (MDREG1: bit 6) allowed segmenting of the TRT, THT, TVX, and TMSYNC registers into 4 and 5 bits each for diagnostic purposes. This is no longer necessary due to the testability enhancements.
s Single-Frame Receive mode is no longer
supported.
s Symbol Control is no longer supported in the MAC.
This function was used for diagnostics purposes to transmit user-controlled data, control and violation symbols to the PHY.
s The HOLD function and associated logic is
eliminated and it is no longer supported.
Miscellaneous Changes from SUPERNET 2
s The `Current Queue Almost Full' (AFULL)
encoding of the QCTRL signals is modified to be asserted for every clock after the AFULL boundary SUPERNET 3 19
AMD
PRELIMINARY SUPERNET 2 chipset. The enhanced encoding is enabled by setting the MENRS bit in the mode register 3 (MDREG3). The encoding of the RS pins is shown on the following table.
RS 5:0
Receive Status pins (outputs) An additional receive status pin has been added to provide more receive information. The encoding of the status pins is fully backward compatible with the
RS5 0 1 1 1 1 1 1 1 1 RS4 X 0 0 0 0 0 0 0 0 RS3 X 0 X 0 0 0 0 0 0 RS2 X 0 0 0 0 1 1 1 1 through 1 1 1 1 1 RS1 X 0 0 1 1 0 0 1 1
RS0 X 0 1 0 1 0 1 0 1
Indicated Status As in SUPERNET 2 FORMAC Plus Reserved Starting Delimiter and non-data symbol received OSM mode: Stripping frame Reserved Reserved Frame Abort Frame Flush Reserved
1
Reserved
QCTRL 2:0
Queue Control pins (outputs) The encoding of the QCTRL pins is as follows:
QCTRL2 QCTRL1 QCTRL0 Indicated Status 0 0 0 (1) Quiescent. (2) Space remains for more data while loading a transmit queue 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Unloading transmit frame from Synchronous Queue Unloading transmit frame from Asynchronous Queue 0 Unloading transmit frame from Asynchronous Queue 1 Reserved Current transmit frame Underrun Current transmit queue full Current transmit queue almost full
Clocking LSCLK
Local Symbol Clock pin (input) The LSCLK is a 25 MHz clock. It is used by the PLC-S and PDX cores.
BCLK
Byte Clock pin (input) The BCLK is a 12.5 MHz clock. It is used by the PLC-S and the MAC cores.
BMCLK
Buffer Memory Clock pin (input) The BMCLK is the clock signal that the MAC core uses for generating the signals to the buffer memory. BMCLK is driven with either a 12.5 or 25 MHz clock signal. If 12.5 MHz operation is desired, then this pin must be tied to BCLK pin. If 25 MHz operation is desired, then this pin must be tied to LSCLK pin.
A, C Indicators
The setting of the A, C indicators has been modified to allow the indicator setting to be selectable in any of the modes: online, online special mode, or external loopback. The A, C indicators can be set as normal, MSC method, or not modified at all. The modified setting of the A, C indicators can be selected by setting the
Slower Buffer Memory Interface
The buffer memory interface has been modified enabling slower SRAMs (35 ns) to be used as buffer memory. This reduces the system cost. The interface is fully backward compatible with the SUPERNET 2 buffer memory interface.
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SUPERNET 3
PRELIMINARY MEIND0 and MEIND1 bits in the mode register 3 (MDREG3).
MEIND1 0 0 MEIND0 0 1 Description Default SUPERNET 2 behavior Set A, C as in ONLINE mode. This overrides OSM status indicator setting (i.e., if MDREG1 bits MMODE2=0, MMODE1=1, MMODE0=0). Set A, C as in OSM mode. This overrides the MMODE2-0 bits in the MDREG2 for the status indicator setting. Do not set the A, C indicators in any mode.
AMD
1
0
1
1
SUPERNET 3
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MEIND[1:0] 00 00 00 00 00 00 01 01 01 01 01 01 01 10 10 10 10 10 10 10 11 OSM 0 0 0 1 1 1 x x x x x x x x x x x x x x x EN_XACT x x x x x x 0 0 0 1 1 1 1 0 0 0 1 1 1 1 x
PRELIMINARY
XDA_XACT x x x x x x x x x x x 0 1 x x x x x 0 1 x XDA 0 x 1 0 x 1 0 x 1 0 x 1 1 0 x 1 0 x 1 1 x DA_INT 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 x A_FLAG 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 C_FLAG 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 0 A_BIT NM 1 1 NM 1 NM NM 1 1 NM 1 NM 1 NM 1 NM NM 1 NM 1 NM C_BIT NM 1 1 NM 1 1 NM 1 1 NM 1 1 1 NM 1 1 NM 1 1 1 NM
where, MEIND[1:0] Bit 4 and 5 of MDREG3 OSM - Bit 14-12 of MDREG1 EN_XACT - Bit 2 of MDREG3 XDA_XACT - Pin 113, is an active low signal. "1" indicates signal is active and "0" indicates signal is inactive XDA - Pin 114, is an active low signal. "1" indicates signal is active and "0" indicates signal is inactive. DA_INT - Internal DA match signal A_FLAG - DA Match Flag C_FLAG - Frame Copied Flag A_BIT - A bit in the End Delimiter C_BIT - C bit in the End Delimiter x - Don't care condition. NM - Not modified by the MAC
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Transmit Queues
ASYNC2 Transmit Queue Not Supported The SUPERNET 3 supports SYNCHRONOUS, and two ASYNCHRONOUS priorities. The ASYNC2 queue is no longer supported. This causes the following changes: 1. TPRI2 (16-bit priority register for asynchronous queue 2) is no longer implemented. 2. EAA2, WPXA2, SWPXA2, RPXA2 registers are no longer implemented. 3. The `Clear Asynchronous Queue 2 Lock' and `Transmit Asynchronous Queue 2' commands are no longer available in the command registers 1 and 2, respectively. The value 0x18 in command register 1 and 0x08 in command register 2 shall not be decoded to any other instruction. These values are reserved. 4. The STEFRMA2, STECFRMA2 and STXABRA2 bits in the upper 16 bits of the status register 1 (ST1U) are reserved and set to zero. Similarly SQLCK2, STXINFLA2, SPCEPDA2, and STBURA2 are reserved and set to zero. 5. The QCTRL[2:0] = 100 encoding is now invalid. This encoding indicated `Request transfer into Asynchronous Queue 2' which is no longer available. The encoding is reserved and shall not be used to indicate any other QCTRL condition. (See NOTE) 6. The HSREQ[2:0] = 111 is now decoded as "Write Request: Asynchronous Queue 1". In FORMAC+ this request indicated a write request to asynchronous queue 2 which is no longer available.
encoding to indicate status of Asynchronous Queue, but instead the QCTRL[2:0] = 011 ("Request transfer into Asynchronous Queue 1") encoding would be indicated by SUPERNET 3 and external logic could be added to invert this encoding to be compatible with FORMAC+. AFULL Encoding of QCTRL Signals Modified
The QCTRL2-0 pins provide the encoded status of the buffer memory transmit queues. The value QCTRL[2:0] = 111, `Current queue almost full', was asserted for one host write cycle in SUPERNET 2. This signal shall now be generated for every host write cycle until the queue becomes full or the almost full threshold is no longer exceeded. This new signal assertion is implemented only if the bit MENAFULL is set in mode register 3 (MDREG3) Transmit Frame Format In SUPERNET 2 transmit frames must consist of aligned data, i.e. all words in the buffer memory must contain four valid bytes, except that the last data word may consist of less than four bytes. This required that the Frame Control (FC) of the frame be written as the most significant byte of the frame data long word. SUPERNET 3 would support an enhanced feature, where in the Frame Control (FC) could be any byte of the frame data long word. The Destination Address (DA) would follow the FC as the next byte in any mode of operation. This feature is enabled only when the bits MENFCLOC (bit 12 & 13) is set in mode register 3 (MDREG3). Upon reset these bits would be both zero and the Frame Control (FC) has to be written as the most significant byte of the frame data long word. The following table describes the decoding of the MENFCLOC bits in the mode register 3 (MDREG 3):
Note: If the encoding HSREQ[2:0] = 111 is used, the SUPERNET 3 would not use the QCTRL[2:0] = 100
If MENFCLOC 13-12 = Case 1: LSB = 0 (MDREG 2 bit 11) Case 1: LSB = 1 (MDREG 2 bit 11) Then FC starts at: Then FC starts at: 00 Byte 1 (MSBYTE) Byte 4 (MSBYTE) Byte 3 Byte 2 01 Byte 2 10 Byte 3 11 Byte 4 (LSBYTE) Byte 1 (LSBYTE)
SUPERNET 3
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PRELIMINARY of transmit frames in modified TAG is identical to TAG mode. The unloading of received frames is different in Modified TAG mode of operation. The format of a receive frame is as shown Figure 1. The first long word in each frame consists of a 16-bit status word and a 16-bit word that gives the length of the frame in bytes. The status/length word is followed by the data words. The location of the first byte in the first long word of data is defined by the byte boundary bits RXFBB1-0 of mode register (MDREG 2). At the end of the frames that make up a receive queue, SUPERNET 3 writes a long word with all bits as a logic 0, which indicates that there is no more data in this queue. The only function of this word is to act as an end delimiter. Note that the MSVALID bit in bit 31 of the status word at the start of the frame is always in the logic 1 state. Also, when another frame follows this queue, it overwrites the end delimiter word with the receive status word of the new frame. After each frame has been written into buffer memory, SUPERNET 3 write the status and frame length at the start of each frame, and places an end-indicator word of all 0's at the end of the queue. Once a frame is completely received, the status bit SRCOMP in status register 2 (ST2U) is set. If the received frame is aborted, the SUPERNET 3 will write the status word indicating the aborted status (bit 30) and the length field bits will be all zero. If the receive queue has an overflow condition during frame reception, the status register bit indicating SRCVOVR in status register 2 (ST2U bit 11), is set high and the frame is aborted. An overflow also sets the MSRABT bit (bit 30) in the receive frame status word of the incomplete frame. The received frames are unloaded by the host from the buffer memory by using the host request pins (HSREQ). The RDATA signal is always in the 0 state and receive frame threshold (RTHR) is not applicable in modified TAG mode for asserting the RDATA pin. If dual receive queue operation is selected (MENDRCV, bit 11 in MDREG 3) then the receive status information would be indicated in the corresponding status register (ST2U for RECV1 and ST3U for RECV2).
Non-Tag Mode of Operation No Longer Supported
The SUPERNET 3 only supports the tag mode of operation for transmit and receive. The non-tag mode of operation is no longer supported. All functionality related to the non-tag mode of operation is removed. This causes the following changes: 1. Bits [7:4] in status register 1 upper (ST1U), indicating `Transmit End of Chain of Frames' (STECFRM-S, A0, A1, A2) are now reserved. They shall be read as zero. 2. Bits [7:4] in status register 1 lower (ST1L), indicating `Transmit Instruction Full' (STXINFL-S, A0, A1, A2) are now reserved. They shall be read as zero. 3. In Command register 2, the commands `Transmit Synchronous Queue' [0x01], `Transmit Asynchronous Queue 0' [0x02], and `Transmit Asynchronous Queue 2' [0x08] are now reserved. These values shall not be decoded to any other instruction. 4. Bit 15 in mode register 2 (MDREG2) indicating Buffer Memory Mode is now decoded differently. This bit shall be read as one upon reset, indicating TAG mode of operation. If programmed to zero, the modified TAG mode of operation will be enabled. This bit selection applies to both receive queues if MENDRCV bit is set in mode register 3 (MDREG 3).
Modified TAG Mode Operation
The SUPERNET 3 will have two modes of host interface to buffer memory. The two modes are distinct and independent ways of accessing the buffer memory depending upon the selection of the TAG mode or modified TAG mode. In TAG mode the SUPERNET 3 provides the local buffer management, i.e the queue pointers are maintained by SUPERNET 3. Modified TAG mode is used when the NON-TAG mode users of FORMAC+ are redesigning for SUPERNET 3. Loading
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31 STATUS WORD 1
16
15 FRAME 1 LENGTH
0
T 1 0 . . . . . . . . . . 0
P3
P2
P1
P0
FRAME 1
STATUS WORD 2
FRAME 2 LENGTH 0 . . . . . . . . . . 0 1 1 1 Aborted Frame Aborted Frame
FRAME 2
STATUS WORD 3 STATUS WORD 4 STATUS WORD 5
FRAME 3 LENGTH FRAME 4 LENGTH FRAME 5 LENGTH
FRAME 5
ALL ZEROs
0
19574A-2
Figure 1. Memory Receive Queue (Modified TAG Mode)
SUPERNET 3
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PRELIMINARY address of the frame. Then the MDRU is loaded from the NP, followed by the MDRL. As soon as the second 16-bit data word is loaded, SUPERNET 3 sets an internal request to move the contents of the MDR to the buffer memory. The MARW is incremented after the write operation is completed. The NP could use the set tag command in CMDREG2 to set the tag bit for the MDR write cycle, however, the tag bit command is valid for one NP write operation only. After the complete frame(s) have been loaded for transmission, the NP has to program the last transmit descriptor pointer (LTDPA1) to be equal to the address of the last descriptor written. Also, the ASYNC1 queue (WPXA1) write pointer needs to be programmed to LTDPA1 + 1. The SUPERNET 3 would assume that the read pointer is at the correct address. The NP should then give an instruction to SUPERNET 3 to transmit the ASYNC1 queue. The SUPERNET 3 would transmit till the read pointer (RPXA1) equals the last transmit descriptor pointer (LTDPA1). The user could load multiple frames before issuing the command. The NP cannot issue more than one transmit command until the SUPERNET 3 indicates the "End of transmit command" status (STECMDA1) in status register 1 - upper (ST1U).
Transmit Command
The SUPERNET 3 provides a feature to control transmission of frames from ASYNC1 queue in both TAG and Modified TAG modes. This feature can be enabled by programming the MENTRCMD (bit 14) in mode register 3 (MDREG3). This feature, when enabled, would wait for the "Transmit Asynchronous Queue1" command. This feature would be applicable only to ASYNC1 queue. The SUPERNET 3 has to be in initialize mode to enable the transmit command feature. Once this is enabled the SUPERNET 3 will not transmit from ASYNC1 queue unless a command in given by the Node Processor. To disable this feature, the SUPERNET 3 has to be in initialize or memory active mode. The read pointer (RPXA1), write pointer (WPXA1) and shadow write pointer (SWPXA1) are under the control of the user. The frames to be transmitted could be loaded by the host into the buffer memory either by using the host request pins, or by using NPDMA pins or by using the MARW and MDR registers. When using the host request pins, the SUPERNET 3 responds to the host request as in any mode, except that the transmit threshold register value would be ignored. IFPC would not monitor the frames being loaded into buffer memory for memory full condition, buffer empty condition etc. After the last data word and descriptor are written to complete the frame, transmit command can be issued to start transmission. When NPMEMRQ pin is used by the NP the address bus and memory control signal lines are placed in the high-impedance state by the SUPERNET 3. This gives the NP free access to load the buffer memory, however, the frames must conform to the format defined. The NP is also responsible in keeping track of Async 1 pointers (WPXA1, RPXA1, LTDPA1) prior to issuing the transmit command. When the NP uses the MARW and MDR to load the buffer memory, it first loads the MARW with the starting
TDAT Loopback
The SUPERNET 3 provides a feature to control the loopback of transmit datapath after the PLC (TDAT) back to the receive data path of the PLC (RDAT). This loopback path is enabled when MDREG3, bit 15 (MENTDLPBK) bit is set to logic "1".
Mode Register 3 (MDREG3)
An additional 16-bit mode register 3 is provided. The new features and modifications are enabled by the setting of the bits in the MDREG3. By default, the register bits are reset to zero. This register can only be written when the SUPERNET 3 is in Initialize or Memory Active modes.
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PRELIMINARY
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMD
LSB MENRS MENXS MENXCT MENAFULL MEIND0 MEIND1
MENQCTRL MENRQAUNLCK MENDAS MENPLCCST MENSGLINT MENDRCV MENFCLOC0 MENFCLOC1 MENTRCMD MENTDLPBK
19574A-3
Figure 2. Register 3 (MDREG3) (NPADDR = 60h)
Bit MENRS (bit 0) MENXS (bit 1) MENXCT (bit 2) MENAFULL (bit 3) MEIND0, MEIND1 (bits 4, 5) MENQCTRL (bit 6) MENRQAUNLCK (bit 7) MENDAS (bit 8)* MENPLCCST (bit 9) MENSGLINT (bit 10) MENDRCV (bit 11) MENFCLOC (bit12,13) MENTRCMD (bit 14) MENTDLPBK (bit 15) Description Enable enhanced Receive status encoding. Enable enhanced Transmit status encoding. Enable EXACT/INEXACT matching. Enable enhanced QCTRL encoding for AFULL. Enables enhanced A, C indicator setting. Enables enhanced QCTRL encoding. Enable Receive Queue Auto Unlock. Enables DAS connections by controlling the MUX. Enables Counter Segmentation Test in PLC block Enables Vectored Interrupt reading. The MINTR4 is used as the Vectored Interrupt. Enables dual receive queue operation. Enables the FC location within the frame data long word. Enables the ASYNC1 queue to transmit only after the command is issued. Enable TDAT to RDAT loopback
* This bit should only be set if the external PHY is available for a DAS configuration.
SUPERNET 3
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PRELIMINARY This method of interrupt generation and processing can be enabled by setting the MENSGLINT (bit 10) in the mode register 3 (MDREG3). If enabled, this mechanism requires the user to read the Interrupt Vector Register (IVR), locate the bit which is set, and read the corresponding interrupt event or status register. Each bit in the IVR is maskable. The interrupts can be unmasked by setting the corresponding bit in the Interrupt Mask Register (IMR). By default, all bits in the IMR are reset (to zero) and all interrupts are masked. The mask register bits are:
Bits bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7-15 Interrupt Source Mask MAC Status register 1 Upper (ST1U) interrupt. Mask MAC Status register 1 Lower (ST1L) interrupt. Mask MAC Status register 2 Upper (ST2U) interrupt. Mask MAC Status register 2 Lower (ST2L) interrupt. Mask MAC Status register 3 Upper (ST3U) interrupt Mask MAC Status register 3 Lower (ST3L) interrupt. PHY Interrupt Event register (INTR_EVENT) interrupt. Reserved. Shall be read as zero.
Address Space
The FORMAC Plus uses seven pins (0-6) and the PLC uses five pins (0-4). The new address space uses eight pins (0-7) with the following decoding:
Address 7:0 00-7F Comment MAC addresses. Up to 128 addresses can be accessed. Currently 127 addresses are used. Full backward compatibility PHY addresses. Currently the PLC has 28 registers defined. This would allow up to 48 addresses to be accessed Address Filter (AF) addresses. Note that the AF currently has ten addresses all of which are read /written by the user PDX address space. There are 16 possible addresses. Reserved for future use
80-AF
B0-CF
D0-DF E0-FF
Interrupts
There are four interrupts: two for the MAC, one for the MAC/BIST, and one for the PHY. The two interrupts for the MAC ensure that the interrupt service routine (ISR) does not have to perform two reads to determine which of the status registers generated the interrupt. The third interrupt is generated when the BIST operations are complete or when the second receive queue has changes in its status. The fourth interrupt indicates the status of the PHY. Interrupt Mechanisms SCALAR: There are four interrupts, two from MAC, one from MAC and BIST, and one from PHY. These interrupts can be tied together externally or serviced separately. This method is the default and is backwards compatible with the SUPERNET 2 interrupt generation and servicing mechanisms. VECTORED: Only one interrupt is monitored (MINTR4), and upon an interrupt being generated, a 16-bit maskable Interrupt Vector Register (IVR) is read. Each bit in the vector register indicates the source of the interrupt. The vector register bits are:
Bits bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7-15 Interrupt Source MAC Status register 1 Upper (ST1U) MAC Status register 1 Lower (ST1L) MAC Status register 2 Upper (ST2U) MAC Status register 2 Lower (ST2L) MAC Status register 3 Upper (ST3U) MAC Status register 3 Lower (ST3L) PHY Interrupt Event register (INTR_EVENT) Reserved. Shall be read as zero.
Once MINTR4 is activated, the corresponding status or event register must be read to enable any further interrupt on MINTR4.
Receive Flush/Transmit Inhibit pin FLXI (input)
The HOFLXI pin is now the FLXI pin and the HOLD function is no longer supported. The functional timing for this pin is as specified in the SUPERNET 2 data book. If the FLUSH function is selected and the pin is asserted by external logic, then the incoming frame is flushed. The buffer memory pointers are not advanced from where they were before the frame was received (i.e. WPR = SWPR). The receive flush pin is asserted by the host to flush the current frame being received based on an external criterion regardless of the address match. This prevents unwanted frames and fragments from occupying receive buffer space and taking up the buffer memory bus bandwidth. If receive threshold is non-zero, then the frame will be flushed only if the pin is asserted before the threshold is crossed. Refer to timing diagram for details. If the TRANSMIT INHIBIT function is selected and the pin is asserted by external logic, then the SUPERNET 3 completes transmitting the current frame
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SUPERNET 3
PRELIMINARY (if transmitting), releases the token, and no further transmissions can occur until the pin is deasserted. During the time that the TRANSMIT INHIBIT function is enabled the network timers and state machines operate normally. As a result of the change to the FLXI pin, which of the two functions is selected depends upon the state of FLXI bits, as follows:
FLXI Pin 0 1 0 1 0 1 0 1 FLXI1 0 0 0 0 1 1 1 1 FLXI0 0 0 1 1 0 0 1 1 Function Implemented Normal Operation Normal Operation Normal Operation FLUSH received frame Normal Operation INHIBIT transmission Reserved Reserved
AMD
2. Command Register 2: The `Enable Receive Single Frame' command (0x40) is no longer a valid command. This is now reserved. 3. Mode Register 1: The `Single-Frame Receive Mode' bit [15] is no longer valid. It is now a reserved bit and shall return a value of zero when read.
Receive Queue Operation
SUPERNET 3 provides a new feature where the user can configure the buffer memory for incoming valid frame into two separate receive queues. The type of frames that each queue would receive is selected in a separate register, the Frame Selection Register (FRSELREG). To enable two receive queues operation, MENDRCV bit in Mode Register 3 (MDREG3) needs to be set. If this bit is cleared, which is the case at the time of reset, then SUPERNET 3 behaves like F+ (i.e only one receive queue is supported, and SUPERNET 3 defaults to Receive Queue 1). If MDREG3 bit 11, MENDRCV and both RECVX3:0 in Frame Selection Register (FRSELREG) is programmed to be "0000" then the SUPERNET 3 would behave like FORMAC+ and the second queue is ignored. However, if one of the RECVX3:0 bits in FRSELREG are programmed to be "0000" then the corresponding queue would receive all frames except the frame type selected for the other queue. Only the second receive queue (i.e. RECV2) can be programmed to be "0000". Programming the RECV1 bits in the Frame Selection Register (FRSELREG) with "0000" and RECV2 bits with a non-zero selection, will result in no data being written in the RECV1 queue. Only the frame type selected by RECV2 bits will be received in the second queue.
Upon reset, the FLXI1:0 bits would read all zeros.
Single Frame Receive Mode
The Single Frame Receive Mode function has been removed from the SUPERNET 3. All associated status, modes and commands are deleted and replaced with reserved. This causes the following changes: 1. Status Register 2 Upper: The `Receive Frame' (SRCVFRM) bit 10 and `Receive Frame Counter Overflow' (SRFRCTOV) bit 9 are now reserved and return a value of zero when read.
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MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB RECV1(0) RECV1(1) RECV1(2) RECV1(3) RECV2(0) RECV2(1) RECV2(2) RECV2(3) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ENXMTADSWAP ENRCVADSWAP
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Figure 3. Frame Selection Register (FRSELREG) Options for selecting frame types under two receive queues operation is as follows:
RECVX3:0 0000 Frame Type Receive all frames except the frame type selected for other queue. RECV1[3:0] bits cannot be programmed as "0000" when RECV2[3:0] bits are non-zero. LLC (includes both Sync. & Async. LLC frames) SMT Non-SMT (includes all non-SMT frames except MAC & Void, MAC & Void frames are received if Promiscuous mode is selected in MDREG1) Implementor MAC Sync. LLC Async. LLC Void Async. LLC & SMT Reserved
19574A-4
The above selection of frames for each queue is made by programming appropriate bits in the Frame Selection register (FRSELREG) and is applicable to only those frames that meet the criteria for copying as defined by ADDET2-0 bits of Mode Register 1 (MDREG1) of SUPERNET 3. The following restrictions apply to frame selection: 1. The same selection is not allowed for both queues. Programming the Frame Selection register with the same selection in both the RECVx3:0 bits would result in SUPERNET 3 operating as a single receive queue mode, and would default to Receive Queue 1. This overrides the MENDRCV bit in the Mode Register 3 (MDREG3). 2. If high level selection option is used for a given frame type, then sub-level selection for the same frame type is not allowed [i.e. If LLC (0001) option is selected for one queue, then Sync. LLC (0110) or Async. LLC (0111) or Async. LLC & SMT options are not allowed for the second queue]. If a selection is made where one frame type is a sub-set of the other frame type, the selection made for RECV1 queue supersedes the selection for RECV2 queue.
0001 0010 0011
0100 0101 0110 0111 1000 1001 1010-1111
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SUPERNET 3
PRELIMINARY The two receive queues will have independent receive FIFO's. There will be two instructions to clear locks on the two receive queues. "Clear Receive Queue Lock" (instruction code 20h) will be for RECV1 and the new instruction" Clear Receive2 Queue Lock "(instruction code 21h) will be for RECV2 queue. "Clear All Queue Locks" command would clear locks on all queues. Clearing the queues would enable further transfer of data received from the corresponding receive FIFO. The received data present in the buffer memory for each queue is indicated by the corresponding RDATA pin. RECV1 data is indicated by RDATA1 and RECV2 data is indicated by RDATA2. If the two receive queue feature is not selected, RDATA1 would indicate received data present in buffer memory. Read requests will not be acknowledged when RDATA pins are inactive. The status bits SRCOMP, SRBMT, SRABT, SRBFL, SRCVOVR of status register 2 upper ST2U (bit 15-11) would be for RECV1 queue. The status bits SRCOMP2, SRBMT2, SRABT2, SRBFL2, SRCVOVR2 of status register 3 upper ST3U (bit 15-11) would be for RECV2 queue. The host interface to read the data received in the second receive queue would use HSREQ2-0 lines and the encoding would be HSREQ[2:0] =001.
AMD
copied into the buffer memory. On the transmit side, the address bits are swapped before the CRC generator, and therefore, the transmitted CRC will be correct for the bit swapped address.
Auto-Unlocking of Receive Queues
The buffer memory receive queue is locked out for any further input when the receive buffer is full (RPRx = WPRx after an increment of WPRx). The lock can be cleared using the node processor commands "clear receive queue lock (20h)" or "clear all queue locks (3Fh)". Once the lock has been cleared, the receive buffer is available for further input. However, the node processor has to clear the lock by using the CMDREG1 to enable reception of frames in the receive buffer. The SUPERNET 3 provides an enhancement feature to allow automatic unlocking of the receive queue based on user-programmable host read count threshold. To enable this feature, MENRQAUNLCK bit in Mode Register 3 (MDREG3) needs to be set. If this bit is cleared, which is the case at the time of reset, the SUPERNET 3 behaves like FORMAC+ (i.e Upon buffer full condition the receive queue is locked for further input and needs a node processor command to clear the lock). If MENRQAUNLCK is enabled, the UNLCKDLY register needs to be programmed with a 8 bit threshold value for each receive queue. Upon receive buffer full condition, the UNLCKDLY value times 4 will be loaded into a counter. The counter will count down for every corresponding host read receive acknowledge. After the number of host read receive acknowledges exceeds the user programmable count (UNLCKDLY) times 4, the SUPERNET 3 would start receiving frames into the corresponding receive buffer queue The SRBFLx bit in ST2U and ST3U would indicate the status of the corresponding receive buffer queue. If this bit is set it indicates that the corresponding receive buffer queue is locked. If the MENRQAUNLCK bit is set in MDREG3 this bit will be auto-cleared after the user programmed delay or on receive buffer empty, otherwise, the node processor has to clear the lock by issuing a command. The auto-unlock will not work if host interface is not used to read the receive queue and the lock can be cleared only by the node processor. This feature can be enabled/disabled in memory active or initialization mode only. Once enabled/disabled the feature applies to both the receive queues (if selected using MENDRCV in MDREG3).
Address Bit Swapping
The SUPERNET 3 provides the necessary logic for swapping the address fields within each frame between FDDI and IEEE Canonical bit order. This involves a bit reversal within each byte of the address field. This feature is user selectable for transmit, receive or both, however, once selected the bit swapping applies to all queues. This is an useful feature for bridging Ethernet to FDDI or for other higher level protocols. Bit 15 of the FRSELREG, ENRCVADSWAP, enables the bit swap on the receive queues. The FC field of the received frame would decide whether the frame has long address or short address. Bit 14 of FRSELREG, ENXMTADSWAP, enables the bit swap of the transmit queues. The FC field of the frame to be transmitted will decide whether the frame to be transmitted has long address or short address. The CRC written into the buffer memory will be the same as received. This logic will not re-generate CRC after bit swapping on the receive queues. The user can set MDREG2 bit 14, STRPFCS, to strip receive FCS and prevent FCS being
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MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
15
RECV1 UNLOCK THRESHOLD
RECV2 UNLOCK THRESHOLD
19574A-5
Figure 4. Delay Register (UNLCKDLY)
Symbol Control
The SUPERNET 3 no longer supports the ability to transmit raw symbols from the Buffer Memory to the PHY. This feature has been removed and the mode bit SYMCTL (bit 5, MDREG2) is now reserved and read as zero.
CFM State Thru_A
Figure Figure 5
Description The internal PHY is the A-port and the external PHY is the B-port. The MAC is placed as shown in the figure. The MENDAS bit in the MDREG3 must be set. The internal PHY is the A-port and the external PHY is the B-port which must be in BYPASS (if PLC). The MAC is placed as shown in the figure. The MENDAS bit in the MDREG3 must be set. The internal PHY is the A-port which must be in BYPASS and the external PHY is the B-port. The MAC is placed as shown in the figure. The MENDAS bit in the MDREG3 must be set. This is the default configuration of the SUPERNET 3. No external PHY is required. The MENDAS bit in the MDREG3 must be reset (by default). This decouples the busses from the external PHY as shown in the figure. The internal PHY (A-port) and the external PHY (B-port) are isolated. This is the default reset state. This configuration is not supported.
Dual Attachment Station (DAS) support
The SUPERNET 3 is a SAS only device which is extensible to a DAS configuration. For a DAS implementation, the MENDAS bit of the MDREG3 must be set and the external PHY must be present. In a SAS configuration, the R9:0 lines are tied to ground and X9:0 lines are driven at all times. The following configurations are supported:
Wrap_A Figure 6
Wrap_B
Figure 7
Wrap_S
Figure 8
Isolated
Thru_B
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SUPERNET 3
PRELIMINARY
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC PHY A Rx Tx PDTR
AMD
RX+, RX- TX+, TX-
X9:0
R9:0
PHY B
19574A-6
PDTR: Phy Data Transmit and Receive Functions
Figure 5. THRU_A Configuration
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC PHY A Rx Tx PDTR RX+, RX- TX+, TX-
X9:0
R9:0
PHY B
19574A-7
PDTR: Phy Data Transmit and Receive Functions
Figure 6. WRAP_A Configuration
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PRELIMINARY
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC PHY A Rx Tx PDTR RX+, RX- TX+, TX-
X9:0
R9:0
PHY B
19574A-8
PDTR: Phy Data Transmit and Receive Functions
Figure 7. WRAP_B Configuration
RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC PHY A Rx Tx PDTR RX+, RX- TX+, TX-
R9:0 X9:0 DAS/SAS Selection Mux
19574A-9
PDTR: Phy Data Transmit and Receive Functions
Figure 8. WRAP_S or SAS Configuration
Changes and Enhancements to PHY
Changes from SUPERNET 2 PLC
BIST enhanced
The Built-In Self Test (BIST) test now covers part of the Elasticity Buffer and Framer logic.
Addition of Scrambler/Descrambler
Scrambler/descrambler is implemented. Scrambling/ descrambling can be disabled either through a pin or through bit 0 in the PLC_CNTRL_C register.
Revision Identification
In SUPERNET 3 PHY, bits 15:11 of the PLC_STATUS_A register will indicate 01111 on a read operation. The Revision ID for SUPERNET 2 PLC-S is 11111.
ENCOFF pin function changed
The function of this pin has changed slightly. In addition to turning off the Encoder (as in SUPERNET 2 PLC), this pin, when asserted, now also turns off the Decoder.
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SUPERNET 3
PRELIMINARY Addition of Scrambler/Descrambler Function to Support Copper PMD This is a description of the Stream-Cipher Scrambler and Descrambler as implemented in the physical layer controller block. The Stream-Cipher Scrambler adds the output of a random generator to the data stream. The purpose is to spread the spectrum and reduce frequency peaks. As a result, higher signal amplitudes can be transmitted over copper that meet the requirements of the FCC and other regulatory agencies. The random generator is the polynomial 211 + 29. The SUPERNET 3 implementation uses a 5-bit parallel technique. The 5-bit output of the random generator is exclusive-ORed with the input to produce scrambled data for transmission. The descrambler has a random generator which is identical to the random generator in the scrambler. The output of this generator is used to decipher the received scrambled data using the same exclusive-OR function. Since both random generators are identical, the output of the receiver random generator is the original data (data XOR Random XOR Random = data). This process is open loop in nature, i.e., the data has no effect on the states of the random generators. Therefore, the descrambler must incorporate synchronization circuitry to preset its state to the same state as the scrambler. Once both random generators start from the same state, they will remain in synchronization. The synchronization circuitry, CREG and HREG registers, are designed to take advantage of the scrambled FDDI line states. During the line states (HLS, QLS, MLS and ILS), CREG and HREG generate known patterns. When the synchronization circuitry detects these patterns, it generates a capture signal and the corresponding output data pattern. CAPTURE controls the random generator. When it is false, the random generator operates open loop. When it is true, the random generator is preset to the deduced output data exclusive-ORed with the input scrambled data. This is equal to the state of the scrambler's random generator. FDDI Line States & Detected Signals
Line State HLS QLS MLS ILS Data Bits 00010000100 00000000000 00000000100 11111111111 Detected Bits 00111001110 00000000000 00000001110 11111111111
AMD
CAPTURE is enabled by SAMPLE, which is enabled by SCRM_RESYNC. SCRM_RESYNC is active when PHY line state is not Active Line State, or Unknown Line State. A false SCRM_RESYNC indicates that the decoded data is correct. Therefore the random generator is synchronized and SAMPLE is set false. SAMPLE is set true when SCRM_RESYNC is true except during the following condition: If two consecutive IDLE bytes and then non-idle bytes are detected when SCRM_RESYNC is true, SAMPLE goes false and stays false for 32 RSCLK cycles. After that the state of SAMPLE depends on SCRM_RESYNC.
Testability
The Test Access Port (TAP) An IEEE 1149.1 boundary-scan architecture is provided for board level testing and diagnostics. All pins are part of the boundary-scan ring except Digital Transmitter/ Receiver pseudo-analog (PECL) pins. The TAP consists of five pins, TCK, TMS, TDI, TDO and TRST. These pins are dedicated connections and may not be used for any other purpose. The boundary-scan architecture includes a TAP controller, an instruction register and instruction decode logic, and a test data register array. The functional description of the TAP that follows is not a complete description of the IEEE boundary-scan architecture. Additional information and a more detailed functional description can be found in the standard document (IEEE Std 1149.1-1990). The description provided here covers the specifics of this particular implementation. TAP Controller The TAP controller is a synchronous 16-state finite state machine which is driven by the TCK and TMS pins. All state transitions of the TAP controller occur at the rising edge of TCK. The transitions are based on the value of TMS at the rising edge of TCK. In the Test-Logic-Reset state the instruction register is initialized with the IDCODE instruction. The TAP controller is forced to the Test-Logic-Reset state whenever a logic 0 is placed on the TRST pin. A system reset has no effect on the TAP controller.
SUPERNET 3
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AMD Instructions Supported
PRELIMINARY significant bit of the instruction register is the bit nearest the TDO output. The encoding of the instructions is as follows:
This section describes the public and private instructions that are supported in this implementation. The instruction register is a 4-bit register. The least
Instruction EXTEST IDCODE SAMPLE TRI_ST RUNBIST SCANBIST BYPASS Description External test Device identification Sample/preload B.S.R. Force outputs to Hi-Z Self-test Manufacturing Testing Bypass register scan
Reg. Selected B.S.R. IDREG B.S.R. Bypass BIST Execution Scan Results Bypass
INST[3:0] 0000 0001 0010 0011 0101 0110 1111
EXTEST Instruction
The EXTEST instruction is used to test board level interconnect and for testing of circuitry external to SUPERNET 3. This instruction selects the Boundary Scan register (BSR) for scanning between TDI and TDO when in the Shift-DR controller state. During execution: 1. SUPERNET 3 outputs are driven from the Parallel Data register (PDR). 2. SUPERNET 3 internal outputs are sampled into the BSR. 3. SUPERNET 3 inputs are sampled into the BSR. 4. SUPERNET 3 internal inputs are driven from the Parallel Data register (PDR).
SAMPLE Instruction
The SAMPLE/PRELOAD instruction is used to observe the normal operation of the SUPERNET 3 without affecting system operation. It is also used to load values into the PDR prior to the selection of another instruction. This instruction selects the BSR for scanning between TDI and TDO during the Shift-DR controller state. During execution: 1. SUPERNET 3 SUPERNET 3. outputs are driven by the
2. SUPERNET 3 internal outputs are sampled into the BSR. 3. SUPERNET 3 inputs are sampled into the BSR. 4. SUPERNET 3 internal inputs are driven from the SUPERNET 3 inputs.
IDCODE Instruction
The IDCODE instruction is provided for access to the manufacturer's identity, the part number, and the version of the SUPERNET 3. This instruction selects the 32-bit identification register for scanning between TDI and TDO in the Shift-DR controller state. The IDCODE instruction is forced into the instruction registers parallel output latches during the Test-Logic-Reset controller state. The 32 bits of the identification register are broken down as follows:
Bits IDREG[31:28] IDREG[27:12] IDREG[11:1] Description Version number (initially 0001) Part number - 2870 (Hex) Manufacturer's ID. The 11-bit manufacturer's ID. for AMD is 00000000001 according to JEDEC publication 106-A. Always set to logic 1. Value = 1287 0003 (Hex)
TRI_ST Instruction
The TRI_ST instruction is provided for easy tri-state of all SUPERNET 3 outputs. This instruction selects the bypass register for scanning between TDI and TDO during the Shift-DR controller state.
RUNBIST Instruction
The RUNBIST instruction is provided for self-test of the SUPERNET 3. This instruction must not be selected during the normal operation of the part. Once the RUNBIST instruction is selected, the BIST operation is enabled by applying a minimum of 65000 TCK clock cycles while in the RUN-TEST/IDLE TAP controller state. Once the minimum number of clock cycles have elapsed, proceed to load the SCANBIST instruction.
IDREG[0] IDREG[31:0]
SCANBIST Instruction
The SCANBIST instruction selects the BIST result register for scanning between TDI and TDO during the Shift-DR controller state. The BIST results can be
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SUPERNET 3
PRELIMINARY shifted out in the SHIFT_DR TAP controller state. The BIST result register is 33 bits in length.
AMD
controller state. The SUPERNET 3 is not otherwise affected by this instruction. Boundary Scan Cells In boundary scan most of the chip input and output latches are linked together to form a scan chain. The main purpose of this is for board level testing. The boundary scan ring order is listed in the following table.
Description scrm encoff ebferr fotoff ulsb lsr[2] lsr[1] lsr[0] rpar r[0] r[1] r[2] r[3] r[4] r[5] r[6] r[7] rcl rcu flxi oe control (1 to enable) xpar x[0] x[1] x[2] x[3] x[4] x[5] x[6]
BYPASS Instruction
The BYPASS instruction is used to bypass the SUPERNET 3 BSR and shorten access times to other devices on a board. This instruction selects the bypass register for scanning between TDI and TDO during the Shift-DR
BSR Cell No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin No. 54 55 56 67 68 69 70 71 72 73 74 75 77 78 79 80 81 82 83 84 N/A 86 87 88 89 90 91 92 93 Pin Type input input output output output output output output input input input input input input input input input input input input - output output output output output output output output
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BSR Cell No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49, 50 51 52 53 54 55, 56 57, 58 59, 60 61, 62 63, 64 65, 66 67, 68 69, 70 71, 72 73, 74 75, 76 77, 78 79, 80 81, 82 83, 84 Pin No. 94 95 96 98 99 100 101 102 103 106 107 108 109 111 112 113 114 116 N/A 117 118 120 121 122 123 124 125 126 128 129 130 131 133 134 135 136 138 139 140
PRELIMINARY
Pin Type output output output output output output output output output output output output output input input input input output - inout output output output output inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout Description x[7] xcl xcu xs[0] xs[1] xs[2] xs[3] rs[0] rs[1] rs[2] rs[3] rs[4] rs[5] xsa_xact xsamat xda_xact xdamat rxafcu oe control (1 to enable) rxafl rxafu[3] rxafu[2] rxafu[1] rxafu[0] rxafl[3] rxafl[2] rxafl[1] rxafl[0] bdtag bdp[0] bdp[1] bdp[2] bdp[3] bd[31] bd[30] bd[29] bd[28] bd[27] bd[26]
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SUPERNET 3
PRELIMINARY
BSR Cell No. 85, 86 87, 88 89, 90 91, 92 94 95, 96 97, 98 99, 100 101, 102 103, 104 105 106 107 108 109, 110 111, 112 113, 114 115, 116 117, 118 119, 120 121, 122 123, 124 125, 126 127, 128 129, 130 131, 132 133, 134 135, 136 137, 138 139, 140 141 142 143 144 145 146 147 148 149 150 Pin No. 142 143 145 146 147 148 150 151 152 153 154 155 N/A 158 159 160 161 162 163 164 165 166 168 169 170 171 173 174 175 176 178 179 180 181 182 183 185 186 187 N/A Pin Type inout inout inout inout inout inout inout inout inout inout output output - output inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout output output input input input output output output output - Description bd[25] bd[24] bd[23] bd[22] bd[21] bd[20] bd[19] bd[18] bd[17] bd[16] cso wr oe control (1 to enable) rd bd[15] bd[14] bd[13] bd[12] bd[11] bd[10] bd[9] bd[8] bd[7] bd[6] bd[5] bd[4] bd[3] bd[2] bd[1] bd[0] rdata2 rdata1 hsreq[2] hsreq[1] hsreq[0] hsack qctrl[2] qctrl[1] qctrl[0] oe control (1 enable)
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SUPERNET 3
39
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BSR Cell No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167, 168 169, 170 171, 172 173, 174 175, 176 177, 178 179, 180 181, 182 183, 184 185, 186 187, 188 189, 190 191, 192 193, 194 195, 196 197, 198 199 200 201 202 203 204 205 206 Pin No. 189 190 191 192 194 195 196 197 199 200 201 202 204 205 206 207 2 3 4 5 6 7 9 10 11 13 14 15 16 17 18 19 N/A 21 22 23 24 25 27 29
PRELIMINARY
Pin Type output output output output output output output output output output output output output output output output inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout - output output output output input input input Description addr[0] addr[1] addr[2] addr[3] addr[4] addr[5] addr[6] addr[7] addr[8] addr[9] addr[10] addr[11] addr[12] addr[13] addr[14] addr[15] np[15] np[14] np[13] np[12] np[11] np[10] np[9] np[8] np[7] np[6] np[5] np[4] np[3] np[2] np[1] np[0] oe control (1 to enable) mintr1 (oecell -1 to force 0, 0 to disable) mintr2 (oecell -1 to force 0, 0 to disable) mintr3 (oecell -1 to force 0, 0 to disable) mintr4 (oecell -1 to force 0, 0 to disable) bmclk bclk npmemrq
40
SUPERNET 3
PRELIMINARY
BSR Cell No. 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 Pin No. 30 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin Type output output input input input input input input input input input input input input input input Description npmemack ready (oecell -1 to force 0, 0 to disable) r/w ds csi lsclk npa[7] npa[6] npa[5] npa[4] npa[3] npa[2] npa[1] npa[0] npmode rst
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Built-In Self Test (BIST) The BIST feature of the SUPERNET 3 is provided to ease board and system level testing, as well as our own manufacturing testing. This feature can be accessed through the TAP as well as the system interface. It is expected that board level testing will use the TAP interface, while system level testing will not have access to the TAP interface and will need to run BIST through the system interface. There are two functional units in the SUPERNET 3 that are tested with BIST. These are the AF CAM core and the enhanced PHY. The BIST testing of the two functional units is available through the node processor interface. See the AF specification for a description of how to run the BIST for the AF. The enhanced PHY BIST is run using the PHY BIST access as described in the SUPERNET 2 PLC data sheet.
Function Internal PLC BIST Address Filter BIST SCANBIST BIST Signature (hex) 5B6B 0553 1 5B6B 0553
DISCRY function no longer supported Setting the DISCRY bit in mode register 1 (MDREG1, bit 6) permitted testing the operation of certain internal timers such as TRT, THT, TVX, and TMSYNC by breaking them into smaller segments. With the enhanced testability features of SUPERNET 3, the DISCRY function is no longer provided. The bit 6 of mode register 1 (MDREG1) is reserved and shall return a value of zero when read.
Summary of Changes to Status and Mode Registers
The following is the summary of changes. The bits in the register which are shaded indicate change from SUPERNET 2. All reserved bits shall be read as zero except where noted.
SUPERNET 3
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MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB STEFRMS STEFRMA0 STEFRMA1 RESERVED RESERVED RESERVED STECMDA1 RESERVED STEXDONS STBFLA STBFLS STXABRS STXABRA0 STXABRA1 RESERVED SXMTABT
15
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-10
Figure 9. Status Register 1 - Upper 16 Bits (ST1U) (NPADDR = 00h)
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB SQLCKS SQLCKA0 SQLCKA1 RESERVED RESERVED RESERVED RESERVED RESERVED SPCEPDS SPCEPDA0 SPCEPDA1 RESERVED STBURAS STBURA0 STBURA1 RESERVED
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-11
Figure 10. Status Register 1 - Lower 16 Bits (ST1L) (NPADDR = 01h) 42 SUPERNET 3
PRELIMINARY
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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LSB SOTRBEC SMYBEC SBEC SLOCLM SHICLM SMYCLM SCLM SERRSF SNFSLD RESERVED RESERVED SRCVOVR SRBFL SRABT SRBMT SRCOMP
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-12
Figure 11. Status Register 2 - Upper 16 Bits (ST2U) (NPADDR = 02h)
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB SRNGOP SMULTDA STKERR STKISS STUXEXP STRTEXP SMISFRM SADET SPHINV SLSTCTR SERRCTR SFRMCTR SSIFG SDUPCLM STRTEXR SESTRIPTK
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-13
Figure 12. Status Register 2 - Lower 16 Bits (ST2L) (NPADDR = 03h) SUPERNET 3 43
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MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB HOFLXI0 HOFLXI1 FULL/HALF LOCKTX EXGPA0 EXGPA1 DISCRY SELRA ADDET0 ADDET1 ADDET2 SELSA MMODE0 MMODE1 MMODE2 SNGLFRM
15
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-14
Figure 13. Mode Register 1 (MDREG1) (NPADDR = 10h)
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB AFULL0 AFULL1 AFULL2 AFULL3 RCVERR RESERVED SYNPRQ ENNPRQ ENHSRQ RXFBB0 RXFBB1 LSB PARITY CHKPAR STRPFCS RCVMODE
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-15
Figure 14. Mode Register 2 (MDREG2) (NPADDR = 20h) 44 SUPERNET 3
PRELIMINARY
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Status Register 3 (ST3U & ST3L)
A 32-bit read only register, designated ST3, and a 32 bit read/write register, designated IMSK3, has been added in SUPERNET 3. This register is dedicated to status handling and interrupt reporting. Any of the bits in this status register can be used generate an interrupt. The bits in ST3 may be masked by the interrupt mask registers (IMSK3) for complete control of the interrupt conditions. ST3 has status bits associated with receive
operation for RECV2 queue, status of internal CAM match operation, and BIST operation for the various sub-blocks of the SUPERNET 3. All status bits except SRBMT2 and SRBFL2 are auto-cleared on reading the register. The remaining bits are set/reset depending upon the state of the monitored conditions. Refer to Interrupt Mechanisms for more detailed information regarding interrupt handling.
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
SRQUNLCK1 SRQUNLCK2 SRPERRQ1 SRPERRQ2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SRCVOVR2 SRBFL2 SRABT2 SRBMT2 SRCOMP2
19574A-16
Figure 15. Status Register 3 - Upper 16 Bits (ST3U) (NPADDR = 61h)
SUPERNET 3
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MSB 15 14 13 12 11 10 9
PRELIMINARY
LSB 8 7 6 5 4 3 2 1 0 AF_BIST_DONE PLC_BIT_DONE RESERVED RESERVED SICAMDAMAT SICAMDAXACT SICAMSAMAT SICAMSAXACT RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
19574A-17
Figure 16. Status Register 3 - Lower 16 Bits (ST3L) (NPADDR = 62h) The following bits are in ST3U (the upper half of ST3). Status Receive Complete (Receive Queue 2) SRCOMP2 (bit 15) This bit is set at the completion of a frame reception following the writing of the frame status and length. Receive frames that are aborted set this bit, but flushed frames do not. This is valid in tag and modified tag mode. Status Receive Buffer Empty (Receive Queue 2) SRBMT2 (bit 14) This bit is set when the receive buffer is empty (i.e. RPR2 = WPR2 after an increment of RPR), and is reset when frames are in the receive buffer. This bit is not auto-cleared when read. An interrupt is generated due to setting of this bit when read from the receive queue is attempted while the receive buffer is empty. Status Receive Abort (Receive Queue 2) SRABT2 (bit 13) The SRABT2 bit is set when the frame being received is aborted. Frames that normally would be flushed but are aborted due to threshold criterion in tag mode would set this bit. Status Receive Buffer Full (Receive Queue 2) SRBFL2 (bit 12) This bit is set when the receive buffer is full (RPR2 = WPR2 after an increment of WPR2). The buffer-memory receive queue is then locked for further input. SRBFL2 can be cleared using the clear receive queue lock (20h) or clear all queue locks (3fh) commands, or by using the auto-unlock feature. Status Receive FIFO Overflow (Receive Queue 2 ) SRCVOVR2 (bit 11) This bit when set, indicates that the SUPERNET 3 receive 2 FIFO has overflowed and receive data has been lost. This condition may occur during the receive buffer full state. SUPERNET 3 will not set the framestatus C indicator (frame copied) on repeated frames when this bit is set. Reserved (bit 10-bit 4) These bits are reserved for future use. Some of these reserved bits may read zero or one and the user should ignore these bits. The corresponding mask register bits should be programmed to mask out the interrupts from these bits.
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SUPERNET 3
PRELIMINARY Status Receive Parity Error Queue 2 SRPERRQ2 (bit 3) This bit is set when there is parity error in the data received in queue 2. Status Receive Parity Error Queue 1 SRPERRQ2 (bit 2) This bit is set when there is parity error in the data received in queue 1. Status Receive Queue 2 Unlocked SRQUNLCK2 (bit 1) This bit is set when the auto-unlock feature unlocks the Receive Queue 2 lock due to buffer full condition. Once the unlock threshold is crossed due the host read operation, the SUPERNET 3 will clear the lock on the receive queue 2 and enable the queue for further input. Status Receive Queue 1 Unlocked SRQUNLCK2 (bit 0) This bit is set when the auto-unlock feature unlocks the Receive Queue 1 lock due to buffer full condition. Once the unlock threshold is crossed due the host read operation, the SUPERNET 3 will clear the lock on the receive queue 1 and enable the queue for further input. The following bits are in ST3L (the lower half of ST3). Reserved (bit 15-bit 8) These bits are reserved for future use. Some of these reserved bits may read zero or one and the user should ignore these bits. The corresponding mask register bits should be programmed to mask out the interrupts from these bits. Status Internal CAM Source Address Exact Match. SICAMSAXACT (bit 7) This bit when set indicates that the source address of the incoming frame exactly matches an entry in the internal CAM. This bit is useful for monitoring frame reception and internal CAM operation. Status Internal CAM Source Address Match SICAMSAMAT (bit 6) This bit when set indicates that the source address of the incoming frame matches an entry in the internal
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CAM based on the internal CAM match logic. This bit is useful for monitoring frame reception and internal CAM operation. Status Internal CAM Destination Address Exact Match SICAMDAXACT (bit 5) This bit when set indicates that the received frame DA exactly matches an entry in the internal CAM. This bit is useful for monitoring frame reception and internal CAM operation. Status Internal CAM Destination Address Match SICAMDAMAT (bit 4) This bit when set indicates that the received frame DA matches an entry in the internal CAM based in the internal CAM match logic. This bit is useful for monitoring frame reception and internal CAM operation. Reserved (bit 3) This bit is reserved for future use. The bit may read zero or one and the user should ignore this bit. The corresponding mask register bit should be programmed to mask out the interrupts from this bit. Reserved (bit 2) This bit is reserved for future use. The bit may read zero or one and the user should ignore this bit. The corresponding mask register bit should be programmed to mask out the interrupts from this bit. Status Physical Layer Controller BIST Done PLC_BIST_DONE (bit 1) This bit when set indicates that the PLC BIST is complete. Status Address Filter BIST Done AF_BIST_DONE (bit 0) This bit when set indicates that Address Filter (Internal CAM) BIST is complete.
SUPERNET 3
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PRELIMINARY
SACL SPECIAL FRAME AREA EACB RPR1 RECEIVE QUEUE 1 EARV1 SWPR1 WPR1 SABC
RPXS SYNCHRONOUS QUEUE (TRANSMIT) EAS RPXA0 ASYNCHRONOUS QUEUE 0 (TRANSMIT) EAA0 SWPXA0 WPXA0 SWPXS WPXS
RPXA1 ASYNCHRONOUS QUEUE 1 (TRANSMIT) EAA1 RPX2 RECEIVE QUEUE 2 EARV2 SWPX2 WPR2
19574A-18
SWPXA1 WPXA1
Figure 17. Buffer Memory Queue Organization
Parity Generation and Checking
The SUPERNET 3 will have the following sequence of parity generation and checking: Transmit Path: The parity, (even or odd) will be checked at the buffer memory interface (BDP pins). Even parity will be regenerated at the MAC--external PHY interface. Receive Path: Parity (even or odd) will be generated at the buffer memory interface. Even parity will be checked at the external PHY (R Bus) interface, if ENA_PAR_CHK (bit 10) in PLC_CNTRL_A register is set.
Node Processor Synchronous Mode Operation
The NPMODE pin (external pin) must be strapped high to select SUPERNET 3 synchronous operation and strapped low to select SUPERNET 3 asynchronous operation. There are two possible methods of synchronous operation of the SUPERNET 3: 1. BMCLK frequency equals BCLK frequency. (i.e. 12.5 MHz), and both clocks must be in phase. 2. BMCLK operates at twice BCLK (i.e. BMCLK = 25 MHz), and both clocks must be in phase.
48
SUPERNET 3
PRELIMINARY In either method, the DS is ignored and should be inactive (HIGH) during all synchronous accesses. The read cycle is initiated by asserting the CSI, NPADDR, NPRW signal which is sampled by the rising edge of the clock. The NPRW signal should be high for read and low for write. At least one clock cycle after the sampling edge, the SUPERNET 3 will begin to drive the NP bus, and this allow the chip driving the NP bus in the previous read or write cycle time to tristate the NP bus. After the next rising edge of clock (the second rising edge after the assertion of CSI) the data on the NP bus will be valid and the READY signal will be asserted. The data will remain valid until the second rising edge of clock after the de-assertion of CSI. The SUPERNET 3 will tristate the NP bus within 1/2 clock cycle after this clock edge. Regardless of how many clock cycles are needed for executing any SUPERNET 3 instruction, READY stays active only for one clock cycle. A write cycle is very similar to the read cycle. The principal difference are as follows: 1. The NPRW signal must be low while CSI is asserted. 2. The data written must be valid on the second rising edge of clock after CSI is asserted and remain valid until the next rising edge of the clock and READY signal goes active (i.e. LOW). Regardless of how many clock cycles are needed for executing any SUPERNET 3 instruction, READY stays active only for one clock cycle. The Node Processor must tristate the NP bus within one half clock period after the second rising edge after the assertion of CSI. The Node Processor can extend the write cycle and the time it has to tristate the NP bus by delaying the de-assertion of CSI signal. All register access is complete in two cycles and READY is asserted at the positive edge of the second clock cycle. An exception is for MDR accesses that may take more than two clock cycles, at which point the assertion of READY is deferred until the last clock period of the execution cycle. Regardless of how many clock cycles are needed for executing any SUPERNET 3 instruction, READY stays active only for one clock cycle. Refer to timing diagrams in specifications for details. The assertion of READY signal could be delayed during MDR accesses by "n" multiples of clock period.
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subsequent external source address match is recognized. It must be asserted and deasserted in an identical fashion to the XDAMAT pin. This input is used in conjunction with the XDAMAT pin as follows:
Match XDA_XACT and XDAMAT XDA_XACT and XDAMAT XDA_XACT and XDAMAT XDA_XACT and XDAMAT Action A, C indicators set and frame copied*. Invalid combination. Ignored by MAC. A, C indicators not set and frame copied. No action.
*Frame is copied if valid frame or if in promiscuous or limited promiscuous mode. In OSM, the A, C indicators are set according to the OSM rules if both bit 4 and bit 5 (MEIND0,1) of MDREG3 are not set.
The XDA_XACT pin, which is generated by the external AF, is logically ORed with the "af_dax" output signal generated by the internal AF logic. This pin is enabled only if the MENXACT bit in the mode register 3 (MDREG3) is set. This pin should be tied high (VCC) when external address detection (an external AF) is not used. XSA_XACT External Source Address Exact Match (input, active low) This input indicates whether the external source address match was exact (low) or inexact (high). This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a subsequent external source address match is recognized. It must be asserted and deasserted in an identical fashion to the XSAMAT pin. This input is used in conjunction with the XSAMAT pin as follows:
Match XSA_XACT and XSAMAT XSA_XACT and XSAMAT XSA_XACT and XSAMAT XSA_XACT and XSAMAT Action Frame stripped. Invalid combination. Ignored by MAC. Frame not stripped. No action.
Address Filter (AF) Support
XDA_XACT and XSA_XACT input signals are provided for the external CAM. XDA_XACT External Destination Address Exact Match (input, active low) This input indicates whether the external address match was exact (low) or inexact (high). This input should remain asserted for at least one BCLK cycle, and must be deasserted for at least one BCLK cycle before a
The XSA_XACT pin which is generated by the external AF is logically ORed with the "af_sax" output signal generated by the internal AF logic. This pin is enabled only if the MENXACT bit in the mode register 3 (MDREG3) is set. This pin should be tied high (VCC) when external address detection (an external AF) is not used.
Introduction
The Address Filter (AF) is a functional block that extends the group and/or individual MAC address recognition capabilities of the core FDDI MAC. The AF 49
SUPERNET 3
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PRELIMINARY then issues a command to the AF to perform the comparison operation. The AF ensures that the node processor commanded comparison does not interfere with a comparison from the MAC receive data bus. The AF indicates the result of the comparison to the node processor in the status register. To perform any comparison operations, comparands must be written into the CAM of the AF. The node processor performs this operation. Writing a comparand to the CAM in the AF is done by loading the new comparand into the node processor comparand registers. The node processor then loads a 48-bit mask associated with this comparand by loading the mask into the node processor mask registers. Finally, the node processor loads the personality associated with this comparand by loading the node processor personality register. The node processor now completes the operation by issuing a command to write into the CAM through the command register. The status register reflects the current state of the operation, indicating when the AF is busy or full. Once completed, the comparand is available for comparison operations through both the node processor and MAC receive bus interfaces. Additional comparands may be loaded by repeating this operation until no empty locations remain in the CAM. The AF also provides a mechanism to remove entries from the CAM. This process is called invalidation. To invalidate an entry in the AF, the node processor will load the contents of the CAM that are to be invalidated into the node processor comparand registers. The node processor then issues an instruction to find the entry in the CAM through the command register. When it is determined that the entry that has been found is the one to be deleted, the node processor issues a command to invalidate the entry. Since it is possible that more than one entry in the AF may match the comparand, the AF indicates when a multiple match occurs. When this occurs, the node processor may temporarily prevent an entry in the AF from participating in find commands issued by the node processor until the correct entry is found. The status register indicates when the AF is not busy, i.e., when operations are complete. There is one more function of the AF that allows the entire CAM to be invalidated in a single operation. The node processor may issue an instruction to invalidate the entire CAM through the command register.
recognizes both source and destination addresses, extending the strip and copy functions of the core FDDI MAC. The AF is a content addressable memory (CAM) that contains 32 entries. Each entry consists of a 48-bit comparand, a 48-bit mask and a 6-bit "personality." The comparand holds the MAC addresses (individual and/or group addresses) for which to look in frames received by the MAC. The mask identifies those bits that are to participate in the address comparison. The personality holds information pertaining to the comparand such as its validity, whether it is a source or destination address, and whether a match by this comparand is to be considered exact. The AF provides quasi-parallel operation, allowing simultaneous manipulation of the CAM from the node processor interface and address matching from the FDDI MAC receive bus interface. The AF receives a byte-wide data stream from the FDDI MAC receive bus as well as the necessary control information to identify the location of the source and destination addresses in the byte stream. It provides an indication of source and destination match and exact match to the FDDI MAC. The AF also has a 16-bit wide interface to the node processor bus. This interface allows the node processor access to the AF data registers and the command and status registers.
Function of the Address Filter
The AF performs the function of matching source and destination addresses presented on the receive data bus and indicating such matches to the MAC. The MAC uses this information in such decisions as stripping frames, copying frames and setting frame status indicators. The AF also matches addresses presented through the node processor interface and indicates these matches in the status register. This allows the node processor to efficiently manage the contents of the AF. To perform the function of matching addresses from the receive data bus, the AF loads bytes from the receive data bus into a comparand register. The MAC indicates the bytes to be loaded. Once the AF receives this indication from the MAC, the AF loads six consecutive bytes into the comparand register. Upon loading the comparand register, the AF performs a parallel comparison of all the valid CAM entries in the AF with the comparand register. The AF then indicates the result of this comparison to the MAC. During AF address comparision operation from the received data bus, the node processor interface operations are ignored, and the ERROR bit, along with the DONE bit, is set in the status register. To perform the function of matching addresses from the node processor interface, the node processor loads six bytes of information, two bytes at a time, into the node processor comparand registers. The node processor 50
Node Processor Registers
There are ten registers in the node processor interface of the AF. They are the command register, the status register, the built-in self test signature register, the personality register, three comparand registers and three mask registers.
SUPERNET 3
PRELIMINARY Command Register (AFCMD) The command register is a 16-bit register that may be read and written through the node processor interface. Writing to this register causes the AF to perform the commanded operation. All data necessary for an
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operation must be set up in the appropriate registers before the command being issued for an operation. This register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset.
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB INST(0) INST(1) INST(2) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
19574A-19
Figure 18. Command Register Reserved (bits 15:3) Reserved These bits are reserved for future use. These bits will always read back as zeroes. INST (bits 2:0) Instruction These bits are the encoded instructions to the AF. When these bits are written, the AF is commanded to perform the associated function. The encoding of the instructions is presented in the table below. These bits will read back the last data that was written to this register.
SUPERNET 3
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INST 2:0 000
PRELIMINARY
Function Invalidate CAM: This function invalidates all entries in the CAM. The DONE, FULL, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. The DONE and EMPTY bits in the status register will be set upon completion of this operation. Write CAM: This function writes the contents of the comparand, mask and personality registers into an empty location in the CAM. The DONE, FULL, FOUND, MULT, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. The DONE bit in the status register will be set upon completion of this operation. The FULL bit in the status register will be set if the CAM is full when this operation is completed. If the FULL bit is set when this command is issued, the write operation will not be performed and the ERROR bit in the status register will be set. Otherwise, the ERROR bit will be cleared. Read CAM: This function causes the contents of the CAM entry matching the comparand (indicated by the FOUND bit in the status register after a FIND command) to be written to the comparand, mask and personality registers in the node processor interface. If more than one entry matches the comparand (indicated by the MULT bit in the status register), one of the entries will be chosen arbitrarily. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE bit in the status register will be set. The ERROR bit will be set if this operation is attempted while the CAM is empty or if the FOUND bit is not set. Run BIST: This function causes the AF to initiate its built-in self test. The contents of the CAM, including all of its registers, may be modified by the operation of this self test. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE and BISTDONE bits in the status register will be set. Other status bits may be in arbitrary states. The AF must be reset after BIST is completed to return it to a known state before performing any other operations on the AF. Find: This function causes the AF to perform a parallel comparison of the comparand registers with the contents of the CAM. CAM entries that have the SKIP bit set will not match the comparand. The node processor mask registers do not participate in this operation. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE bit in the status register will be set and the FOUND, MULT and EXACT bits will be updated with the appropriate status of the operation. Invalidate: This function operates on the result of the last "Find" instruction, above, and sets the INVALID bit in the personality of the first matching entry in the CAM. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE bit in the status register will be set. The EMPTY bit will be updated with the appropriate status after the operation. The ERROR bit will be set if this operation is attempted while the FOUND bit is not set. Otherwise, the ERROR bit will remain cleared. Skip: This function operates on the result of the latest "Find" operation and causes the AF to set the SKIP bit in the personality of the first matching CAM entry. The SKIP bit will be set in the same entry that will be read by issuing a "Read CAM" instruction. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE bit in the status register will be set. The ERROR bit will be set if this operation is attempted while the FOUND bit is not set. Otherwise, the ERROR bit will remain cleared. Clear all SKIP bits: This function causes the CAM to clear all SKIP bits. The DONE, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this command is issued. Upon completion of this operation, the DONE bit in the status register will be set.
001
010
011
100
101
110
111
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SUPERNET 3
PRELIMINARY Status Register (AFSTAT) The status register is a 16-bit register that may be read and written through the node processor interface. This
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register contains the status of the AF. All bits of the status register are static; they are not cleared after a read operation.
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB RESERVED RESERVED RESERVED RESERVED RESERVED
REV. NUMBER 0 REV. NUMBER 1 REV. NUMBER 2 BISTDONE EMPTY ERROR MULT EXACT FOUND FULL DONE
Reserved bits are read as zero unless otherwise stated.
19574A-20
Figure 19. Status Register DONE (bit 15) Done Indicator The DONE bit indicates to the node processor that the AF is finished performing a previously commanded operation. The node processor must not issue any command to the AF when this bit is not set. This bit may be used to generate an interrupt to the node processor indicating the completion of an operation. FULL (bit 14) CAM Full This bit indicates the state of the CAM array. When this bit is set, there are no invalid CAM entries, i.e., all CAM entries have their VALID bit set. When this is reset, there is at least one invalid entry in the CAM. If this bit is set, the AF should not be commanded to "Write CAM." If that instruction is issued when this bit is set, the operation will not be performed. FOUND (bit 13) Comparand Found in CAM This bit indicates the result of a "Find" operation. When set, this bit indicates that the data in the comparand register matches at least one entry in the CAM (as masked by the mask entries). If this bit is reset, this bit indicates that no entry in the CAM matches the data in the comparand register. This bit is cleared as a result of a "Skip" or "Invalidate" operation. EXACT (bit 12) Exact Match This bit reflects the result of a "Find" operation. When set, this bit indicates that at least one matching CAM entry (as masked by its mask entry) has the DAX bit set in its personality byte. If this bit is reset, no matching CAM entries have the DAX bit set in the corresponding personality bytes. This bit is cleared as a result of a "Skip" or "Invalidate" operation.
Note: The ERROR bit in the status register will not be set if a "Write CAM" instruction is issued when this bit is set. The user has to read this bit status before attempting to write an entry into the CAM.
SUPERNET 3
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AMD MULT (bit 11) Multiple Match
PRELIMINARY Reserved (bits 4:0) Reserved These bits are reserved for future use. These bits should always be written with zeroes to ensure compatibility with future revisions of the AF. These bits will always read back as zeroes. BIST Signature Register (AFBIST) This is a 16-bit register that may be read and written by the node processor. After the initiation of BIST, this register will hold the signature resulting from the execution of built-in self test when the BISTDONE bit is set in the status register. Comparand Registers (AFCOMP2:0) The comparand registers are 16-bit registers that may be read and written by the node processor. AFCOMP0 corresponds to bits 15:0 of the CAM entry. AFCOMP1 corresponds to bits 31:16 of the CAM entry. AFCOMP2 corresponds to bits 47:32 of the CAM entry. This register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. This register will be updated with the contents of the first matching entry in the CAM if a "Read CAM" instruction is issued to the command register while the FOUND bit is set.
This bit reflects the result of a "Find" operation. This bit has meaning only if the FOUND bit is set. If this bit is set, it indicates that more than one entry in the CAM matches the value in the node processor comparand register. This bit is cleared as a result of a "Skip" or "Invalidate" operation. ERROR (bit 10) Error This bit indicates that an improper operation was attempted. This bit will be set for the following condtions: If an attempt is made to issue the "Read CAM" instruction while the EMPTY bit is set. If the "Invalidate" or "Skip" instructions are issued and the FOUND bit is not set. If the Node Processor command operation is ignored due to Receive Bus address match operation. EMPTY (bit 9) CAM EMPTY This bit reflects the state of the CAM array. This bit will be set if all entries in the CAM have their VALID bits reset. EMPTY bit will be reset after write CAM command. BISTDONE (bit 8) BIST Complete This bit reflects the state of the built-in self test (BIST). This bit will be cleared after reset, while BIST is running and after an instruction is issued to the command register. It will be set once BIST is complete. Revision Number Bits 7, 6 and 5 provide a three-bit binary value that indicates the revision number of the Address Filter.
FC
DA (47:32) DA (31:16)
DA (15:0)
SA
AFCOMP2
AFCOMP1 AFCOMP0
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MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMD
LSB AFCOMP(32) AFCOMP(33) AFCOMP(34) AFCOMP(35) AFCOMP(36) AFCOMP(37) AFCOMP(38) AFCOMP(39) AFCOMP(40) AFCOMP(41) AFCOMP(42) AFCOMP(43) AFCOMP(44) AFCOMP(45) AFCOMP(46) AFCOMP(47)
19574A-21
Figure 20. Node Processor Comparand Register (AFCOMP2)
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB AFCOMP(16) AFCOMP(17) AFCOMP(18) AFCOMP(19) AFCOMP(20) AFCOMP(21) AFCOMP(22) AFCOMP(23) AFCOMP(24) AFCOMP(25) AFCOMP(26) AFCOMP(27) AFCOMP(28) AFCOMP(29) AFCOMP(30) AFCOMP(31)
19574A-22
Figure 21. Node Processor Comparand Register (AFCOMP1) SUPERNET 3 55
AMD
MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB AFCOMP(0) AFCOMP(1) AFCOMP(2) AFCOMP(3) AFCOMP(4) AFCOMP(5) AFCOMP(6) AFCOMP(7) AFCOMP(8) AFCOMP(9) AFCOMP(10) AFCOMP(11) AFCOMP(12) AFCOMP(13) AFCOMP(14) AFCOMP(15)
19574A-23
15
Figure 22. Node Processor Comparand Register (AFCOMP0) Mask Registers (AFMASK2:0) The mask registers are 16-bit registers that may be read and written by the node processor. AFMASK0 corresponds to bits 15:0 of the CAM mask entry. AFMASK1 corresponds to bits 31:16 of the CAM mask entry. AFMASK2 corresponds to bits 47:32 of the CAM mask entry. A "1" written to a bit position in the mask register will enable the corresponding bit in the comparand to participate in the comparison operation. A "0" written to a bit in the mask register will disable, or mask, the corresponding bit in the comparand. A bit that is masked will always match the corresponding bit in a comparison operation. This register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. This register will be updated with the contents of the first matching entry in the CAM if a "Read CAM" instruction is issued to the command register while the FOUND bit is set.
56
SUPERNET 3
PRELIMINARY
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMD
LSB AFMASK(32) AFMASK(33) AFMASK(34) AFMASK(35) AFMASK(36) AFMASK(37) AFMASK(38) AFMASK(39) AFMASK(40) AFMASK(41) AFMASK(42) AFMASK(43) AFMASK(44) AFMASK(45) AFMASK(46) AFMASK(47)
19574A-24
Figure 23. Mask Register (AFMASK2)
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB AFMASK(16) AFMASK(17) AFMASK(18) AFMASK(19) AFMASK(20) AFMASK(21) AFMASK(22) AFMASK(23) AFMASK(24) AFMASK(25) AFMASK(26) AFMASK(27) AFMASK(28) AFMASK(29) AFMASK(30) AFMASK(31)
19574A-25
Figure 24. Mask Register (AFMASK1) SUPERNET 3 57
AMD
MSB
PRELIMINARY
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB AFMASK(0) AFMASK(1) AFMASK(2) AFMASK(3) AFMASK(4) AFMASK(5) AFMASK(6) AFMASK(7) AFMASK(8) AFMASK(9) AFMASK(10) AFMASK(11) AFMASK(12) AFMASK(13) AFMASK(14) AFMASK(15)
19574A-26
15
Figure 25. Mask Register (AFMASK0) Personality Register (AFPERS) The personality register is a 16-bit register that may be read and written by the node processor. This register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. This register will be updated with the contents of the first matching entry in the CAM if a "Read CAM" instruction is issued to the command register while the FOUND bit is set.
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MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMD
LSB VALID DA DAX SA SAX SKIP RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Reserved Bits are Read as Zero Unless Otherwise Stated.
19574A-27
Figure 26. Personality Register Reserved (bits 15:6) Reserved These bits are reserved for future use. These bits should always be written with zeroes to ensure compatibility with future revisions of the AF. These bits will always read back as zeroes. SKIP (bit 5) Skip This Entry This bit prevents the associated entry from indicating a match during a "Find" operation begun through the command register. This bit has no effect on comparisons with comparands received from the MAC interface. SAX (bit 4) Source Address Exact This bit causes the AF to indicate that any comparison matching this CAM entry to a source address will be indicated as being an exact match. An exact match may contain masking done while comparing the entry. Invalid if SA is zero. SA (bit 3) Source Address This bit enables the CAM entry for comparison with source addresses. DAX (bit 2) Destination Address Exact This bit causes the AF to indicate that any comparison matching this CAM entry to a destination address will be indicated as being an exact match. An exact match may contain masking done while comparing the entry. Invalid if DA is zero. DA (bit 1) Destination Address This bit enables the CAM entry for comparison with destination addresses. Valid (bit 0) CAM Entry Valid This bit indicates that the CAM entry is valid and is enabled for comparisons with addresses indicated by the SA and DA bits.
SUPERNET 3
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AMD Node Processor Register Address Map
PRELIMINARY network. The MAC signals the AF at the beginning of the source and/or destination address through the MAC address state machine's state variable. The AF uses this state variable to load six consecutive bytes into the MAC comparand register and perform the comparison of the address against the contents of the CAM when the complete address is in the register. The AF signals the MAC with the result of the comparison and if the comparison is exact (as determined by the appropriate bit in the personality byte). The AF will decode the Frame Control (FC) field of the received frame and will not participate in the address match if bit 6 of the FC is zero (indicating a short address frame). MAC Comparand Register This is a 48-bit register that is loaded from the MAC receive data bus. The data arrives one byte at a time and is loaded byte serially into the register. An internal multiplexer is driven by the state variable of the MAC address state machine. Once started, the state machine causes the register to load six consecutive bytes from the receive data bus into the comparand register. Upon completion of the loading of the register, the contents will be transferred to the MAC comparand shadow register for comparison with the contents of the CAM. MAC Comparand Shadow Register The MAC comparand shadow register receives the contents of the MAC comparand register once that register has been loaded with six bytes of address information from the MAC receive data bus. This allows the MAC comparand register to immediately begin loading a subsequent address from the receive data bus without interfering with the comparison function of the AF. Once data has been transferred into the MAC comparand shadow register, the contents of the shadow register are compared with the contents of the CAM.
The registers accessible through the node processor interface are addressed as shown in the table below.
Register Mnemonic AFCMD AFSTAT AFBIST AFCOMP2 AFCOMP1 AFCOMP0 AFMASK2 AFMASK1 AFMASK0 AFPERS Address "b0" "b2" "b4" "b6" "b8" "ba" "bc" "be" "c0" "c2" Register Name Address Filter Command Register Address Filter Status Register Address Filter BIST Signature Address Filter Comparand 2 Register Address Filter Comparand 1 Register Address Filter Comparand 0 Register Address Filter Mask 2 Register Address Filter Mask 1 Register Address Filter Mask 0 Register Address Filter Personality Register
MAC Interface
The AF interfaces to the FDDI MAC through the receive data bus, MAC status and control signals, and the AF match output signals. As described above, the AF loads addresses to be compared as they are received from the
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bclk
rx
cmrx_rbus
cmrx_addrsm_state
cmrx_startdelimeter_rx
cmrx_da_next_done
cmrx_sa_next_done
af_da_match
af_dax
af_sa_match
af_sax
19574A-28
Figure 27. AF-MAC Interface Handshake (Internal Signals)
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AMD
PRELIMINARY The AF will have a serial input and serial output through which the results of the BIST can be shifted. These resuls shall be shifted in response to the appropriate TAP interface signals. The AF BIST execution will depend on signals provided by the TAP controller and will run at a rate determined by the TAP test clock. The clocking of the BIST will be taken care of external to the AF. This can be done by multiplexing the normal AF clock with the test clock during the RUNBIST instruction. The AF BIST implementation shall not require a seed value to be serially shifted in. The minimum number of test clock cycles necessary for the completion of BIST needs to be provided. After the minimum number of clock cycles the AF must hold the results of the BIST constant until requested to shift them out by the TAP controller. Each execution of BIST shall provide the same result and shall not depend on the state of signals received at non-TAP interface signal. The serial BIST operation is begun when the tl_bistena signal from the TAP controller is asserted. This signal must remain asserted for the minimum duration specified to guarantee a valid signature. When the minimum number of clock cycles has passed the tl_bistena signal will be de-asserted and a short time later the tl_bistse signal will be asserted to shift out the contents of the signature register through the af_tdo output. When the tl_bistena signal becomes de-asserted, the signature register should hold its content until the tl_bistena signal is asserted again, or the AF is reset. If the minimum number of clock cycles for the completion of BIST is not met, an intermediate signature will be obtained. This can be used to aid in fault isolation for internal manufacturing testing.
ADDRESS FILTER TEST SPECIFICATION Introduction
The Address Filter (AF) core requires a special set of test patterns to provide adequate fault coverage. The mask and data bits of the AF are similar to an SRAM cell and must be tested with the types of test patterns that are used to test SRAM's. The main fault models that are applied in SRAM testing are the stuck-at fault model, the transition fault model, and the coupling fault model. The stuck-at fault model describes the condition where a cell or line is always 0 or 1 and can't be changed to the opposite state. The transition fault model describes the condition where a cell or line fails to undergo a transition from 0_1 or from 1_0 when it is written. The coupling fault model describes the condition where a write to a cell that causes a transition in that cell, also causes a transition in another cell. In addition to the test necessary for the above fault models, the CAM contains additional personality bits, match logic and a priority encoder that must also be tested. The AF core will be tested through the use of built-in self test (BIST). The patterns that need to be applied to the SRAM portion of the CAM are algorithmic in nature and can be easily implemented with BIST. The components of the AF BIST logic will include a state machine, a data generator, a signature register, and an address generator.
Test Logic Description
This section provides a description of the AF test logic. BIST Operation The BIST feature can be accessed by one of two methods. The first means of access is a serial mode of access meant to be used with an IEEE 1149.1 Test Access Port (TAP) controller. The second means of access is a parallel mode of access using the node processor interface. Each means of access is described further below.
Node Processor Interface
Access to BIST through the node processor interface is provided for board and system level testing. BIST is initiated through this interface by writing the Run BIST instruction to the AFCMD register. The BISTDONE and DONE bits in the AFSTAT register are cleared upon issuing this instruction and the BIST state machine moves from the idle to the operational state. At the completion of self test, the BISTDONE and DONE bits will be set in the AFSTAT register. The DONE bit can be used to generate an interrupt to the node processor indicating the completion of the self test. The result of the self test can be obtained by reading the AFBIST register and comparing it to the known good signature.
TAP Interface
Access to BIST through the TAP interface is provided so that the core can be tested in a product that supports the RUNBIST instruction of the IEEE 1149.1 standard. As such, the implementation of the BIST should conform to all the rules described for the RUNBIST instruction in the standard. Some of these rules apply only to the design of the TAP controller itself, while others affect the implementation of the AF BIST logic. The rules that affect the implementation of the AF BIST logic are summarized below.
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BIST Pattern Requirements
This section presents the pattern requirements that the BIST implementation should try to meet. The implementation should try to meet as many of the requirements as possible, however, overhead considerations may make this goal unattainable. In the case that the requirements are not met, a means of applying these patterns functionally must be found. The functional application of patterns may dictate additional testability requirements in the AF. The pattern requirements are divided into two sections, the first deals with the testing of the portion of the AF that is SRAM-like, the second deals with the testing of the remaining AF logic such as the match logic, priority encoder, exact logic, etc. Pattern requirements for the SRAM-like portion of the AF The following pattern requirements are taken from a paper by Jain and Stroud. Some of the requirements may be architecture specific and may not be necessary. Additional requirements may be necessary depending on the architecture of the AF. This paper describes two algorithms that may be used in the implementation of the BIST test. 1. Each cell must undergo a 0_1 transition and then a 1_0 transition or vice versa. Each cell must be read after each transition. 2. For every pair of physically adjacent cell i and j the test writes cell i with and 1 and cell j with a 0 and then cell i with a 0 and cell j with a 1. It then reads after each write. To consider coupling faults between master/slave bits, cells i and j are written with the same data. 3. Each cell must be read twice after writing a 1 and a 0. 4. Decoder faults should be detected by writing unique data in every memory word and then reading the AF. 5. A special sequence of data patterns should be written and read to detect stuck-at faults in the read column decoder logic. 6. Some memory words should be written and read with data having different logic values on every pair of adjacent input data lines.
Pattern requirements for the non-SRAM portion of the AF The following pattern requirements may be difficult to implement in silicon and may have to be applied functionally. Some of the patterns described in this section can be applied at the same time as the SRAM tests are being applied. The non-SRAM portion of the AF consists of the comparator, the source address exact/inexact match logic, the destination exact/inexact match logic, and the multiple match logic (which includes the priority encoder logic). The stuck-at fault model is the only fault model used in developing the pattern requirements for this portion of the AF. The other fault models discussed earlier were developed for memory arrays and it would not make sense to try to apply them to this section of the AF. Comparator The output of the comparator logic is the 32 match lines for each AF entry. The output of the comparator is further modified by the state of the personality bits. The comparator can be viewed as 32 48-bit wide comparators with one half of the inputs to each comparator supplied by the corresponding mask and data bits for each comparator, and the other half of the inputs to each comparator supplied by the comparand register. For the purpose of describing the data patterns necessary to test each comparator it will be assumed that all valid bits are set, all skip bits are reset and that either the SA or DA bits are set to allow a match operation to be visible outside the AF. The following table summarizes the truth table for a single bit of the comparator: Table 1. Truth Table for the Comparator
MASK 0 1 1 1 1 DATA X 0 0 1 1 COMP X 0 1 0 1 MATCH YES YES NO NO YES
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PRELIMINARY d) Repeat steps a through c but this time use all 1's. At this point half of the XNOR tests (lines 2 and 5 in table 1) have been completed and the AND circuitry has been tested for s@0 faults. Part #2 a) Write each data entry with all 0's. b) Do 48 matches while walking a 1 through a field of 0's in the comparand register. Since a single bit is in error for each match, a match condition should never occur. c) Repeat steps a and b with each data entry being all 1's and walking a 0 through a field of 1's in the comparand. At this point, all the XNOR tests are completed. This also checks for s@1 faults in the AND circuitry since all but a single bit match. This test also tests for the mask bit s@0. Source address exact/inexact logic: The SRAM portion of this logic, namely the storage for the SA and SAX personality bits will be tested by the SRAM tests presented earlier. What remains to be tested is the logic that generates the source address match and the source address match exact logic. The test pattern description that follows does not yet take into account the impact of the SKIP bit since its use hasn't been completely determined as yet. The patterns also assume the existence of an all match indication as described earlier. The following table summarizes the patterns that need to be applied to check each entry match and exact indicators:
1. The stuck-at 1 (s@1) condition in the mask bits for a comparator can be checked by first writing all mask bits to 0's, all data bits to 0's and the comparand register to all 1's. If any single mask bit is s@1, no match will occur otherwise a match will result as can be seen from the first line of table 1. To speed the testing for this condition, all entries can be tested in parallel if an all match indication is provided. All mask and data bits are written with 0's and compared simultaneously with the comparand. Each entry should match resulting in the all match condition. If any mask bit is s@1, the all match condition will not occur and the fault can be detected. 2. The stuck-at 0 (s@0) condition in the mask bits for a comparator are tested by the data patterns shown in the third and fourth lines of table 1. These lines are a subset of the patterns needed to test the XNOR faults that are represented by lines 2 through 5 of table 1. The outputs of the XNOR gates for each bit are all AND'ed together to form the match output of the comparator. The following test description will cover all stuck-at faults for the remainder of the comparator logic. These tests assume that all mask bits are written with 1's and assume the existence of an all match indication. The test is described in two parts: Part #1 a) Write each data entry with all 0's. b) Write the comparand register with all 0's. c) Perform a match operation--should get an all match indication.
Table 2. Patterns necessary for match and exact indicators
SAX 1 0 1 1 VALID 1 1 0 1 SA 1 1 1 0 MATCH[i] 1 1 0 0 EXACT[i] 1 0 0 0 ALL MATCH? YES YES NO NO
The individual match lines for each entry must be OR'd together to determine if a match has occurred. The individual exact match lines must also be OR'd together to determine if an exact match has occurred. The pattern shown in the first line of the table will detect all s@0 faults on the logic that generates each match and exact line for an entry. It will also check for a s@0 fault on the final match and exact outputs. The pattern shown in the second line of the table will check for all s@1 faults arising from the SAX personality bits and will also detect a s@1 fault on the final exact output. The pattern shown in the third line of the table will check for s@1 faults on the VALID personality bits as well as on the final match and exact outputs. The final pattern shown in the fourth line 64
of the table will check for s@1 faults on the SA personality bits as well as on the final match and exact outputs. One could argue that the first pattern is not sufficient to cover all possible s@0 faults in the final OR'ing of the individual match and exact lines since these faults are detected on the assumption of the existence of an all match indication (an all exact indication is also necessary). The all match indicator is used to speed the testing of the AF since all entries can be written with the same values. If someone is uncomfortable with this potential loss in coverage, then an additional 32 patterns are needed that only apply the first pattern of the table to each entry by itself so that only one entry
SUPERNET 3
PRELIMINARY causes the match and exact lines to be asserted. This pattern will take much longer to apply than the minimal set presented in table 2. Destination address exact/inexact logic: Since the destination address matching logic is identical to the source address matching logic, the same test can be applied as described in the previous section of this document. These tests can be applied simultaneously with the source address patterns.
AMD
1. Load the value of the comparand that it is desired to find into the NP comparand register. 2. Write the "Find" instruction into the NP command register. Note: the comparand is not modified by the NP mask registers. 3. Read the NP status register when the DONE bit is set. If the FOUND bit is set, there is at least one matching entry in the AF that does not have its SKIP bit set. If the MULT bit is also set, there is more than one entry that matches the comparand that does not have the SKIP bit set.
PROGRAMMING METHODS
This section provides details of how the AF is intended to be used. This section provides a description of the methods to write entries into the AF, to find entries in the AF and to invalidate entries in the AF.
Invalidating Entries in the AF
In conjunction with managing the contents of the AF, it may be required to remove entries. This process is called "invalidation." To invalidate an entry in the AF, the following steps should be followed. 1. Load the NP comparand register with the value of the AF entry that is to be removed. 2. Write the "Find" instruction into the NP command register. 3. When the DONE bit is set, read the NP status register. Do one of the following: 3a.If the FOUND bit is not set, there is no entry in the AF that matches the comparand that does not have its SKIP bit set. 3b.If the FOUND bit is set and the MULT bit is not set, there is only one entry in the AF that matches the comparand that does not have its SKIP bit set. Write the "Invalidate" instruction into the NP command register. 3c. If the FOUND and MULT bits are set, there is more than one entry in the AF that matches the comparand that does not have its SKIP bit set. If all of these entries should be invalidated, write the "Invalidate" instruction followed by the "Find" instruction into the NP command register repeatedly until the FOUND bit is not set in the NP status register. If only one of the multiple matching entries should be invalidated, write the "Read CAM" instruction to the NP command register, compare the contents read back from the CAM to the desired comparand, mask and personality. If the currently matching AF entry is the one that should be invalidated, write the "Invalidate" instruction to the NP command register. If the currently matching AF entry should not be invalidated, write the "Skip" instruction to the NP command register and repeat the invalidate process from the beginning. 4. Write the "Clear all SKIP" instruction to the NP command register.
Writing Entries into the AF
In order for the AF to perform the function of matching addresses in network frames, the desired addresses must be loaded into the CAM portion of the AF. The following procedure should be followed to accomplish this operation. 1. Write the comparand value into the NP comparand registers. Note that the comparand register will retain any previous value if it is not overwritten. 2. Write the NP mask register if it is desired to mask any portion of the comparand. Note that the mask register will retain any previous value if it is not overwritten. 3. Write the NP personality register with the desired configuration of the SA, SAX, DA and DAX bits. The VALID bit must be set if this entry is to participate in any comparisons (either NP or network). If the VALID bit is not set, this entry may be overwritten when another entry is written to the CAM. The SKIP bit should be cleared if this it will be necessary to find this entry through the NP interface at a later time. Note that the personality register will retain any previous value if it is not overwritten. 4. Write the "Write CAM" instruction into the NP command register. 5. The status register should be read once the DONE bit is set to ensure that the ERROR bit was not set.
Note: The ERROR bit in the status register will not be set if a "Write CAM" instruction is used when this bit is set. The user has to read this bit status before attempting to write an entry into the CAM.
Finding Entries in the AF
Once a number of entries are resident in the AF, it may be necessary to find one or more of them. The process below should be used to perform this operation.
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PRELIMINARY multiplier is referenced to the rising edges of LSCLK only. In order to generate the serial output waveforms conforming to the FDDI specifications, the external reference clock must meet FDDI frequency and stability requirements. Under normal conditions, the frequency of LSCLK must be within the FDDI specified 50 ppm of the received data for the PDX to operate optimally. (Note: The 50 ppm is the tolerance of the crystalcontrolled source.) The TX+/TX- serial outputs comply to the FDDI SMF-PMD jitter allocation and typically contains less than 0.4 ns peak-to-peak jitter at 125 MBaud. The PDX accepts encoded PECL NRZI signal levels at the RX+/RX- inputs and converts them to NRZ format. The receiver circuit recovers data from the input stream by regenerating clocking information embedded in the serial stream. The PDX then clocks the unframed symbol (5 bits) to the RDAT 4-0 interface on the falling edge of RSCLK to the PLC-S core. The PDX receiver uses advanced circuit techniques to extract embedded clock information from the serial input stream and recovers the data. Its operating frequency is established by the reference at LSCLK. The PDX is capable of tracking data correctly within 1000 ppm of LSCLK (exceeds the frequency range defined by the FDDI specification). FDDI 4B5B encoding scheme ensures run-length limitation and adequate transition density of the encoded data stream, while TP-PMD achieves this on a statistical basis through data scrambling. The PDX clock recovery circuit is designed to meet and exceed a worst-case run-length tolerance of 60-bits in order to function correctly with both fiber-optic and twisted-pair PMDs. The actual run-length tolerance is more than 1000 bits due to the unique data recovery technique. The PDX receiver has input jitter tolerance characteristics that meet or exceed the recommendations of Physical Layer Medium Dependent (PMD) FDDI document. Typically, at 125 MBaud (8 ns/bit), the peak-topeak Duty-Cycle Distortion (DCD) tolerance is 1.4 ns, the peak-to-peak Data Dependent Jitter (DDJ) tolerance is 2.2 ns, and the peak-to-peak Random Jitter (RJ) tolerance is 2.27 ns. The total combined peak-to-peak jitter tolerance is typically 5 ns with bit error rate (BER) better than 2.5 X 10-10.
PDX FUNCTIONAL DISCRIPTION Introduction
The PDX is a digital CMOS core that is used in SUPERNET 3. It employs new circuit techniques to achieve clock and data recovery. Traditionally, Phase-Locked-Loops (PLL) are used for the purpose of clock recovery in data communication areas. There are both analog and digital versions of the PLL components such as phase detector, filter, charge pump. A traditional PLL always contains a voltage-controlled oscillator (VCO) to regenerate a clock which is frequency synchronized to and phase aligned with the received data. The PDX employs techniques that are significantly different from the traditional PLL. Not only are the control functions completely digital, the VCO function is also replaced by a proprietary delay-line technique. The result is a highly integratable core which can be manufactured in a standard digital CMOS process. The PDX transmitter serializes encoded NRZ symbols. The clock multiplier circuit generates a bit rate (125 MHz) clock from the LSCLK reference. The serial data stream is converted into NRZI for output to the PMD transceiver. The PDX receiver uses the clock recovery circuit to extract clock information from the received data. The recovered clock is used to operate the serial-to-parallel conversion logic.
PDX FUNCTIONAL DESCRIPTION
The PDX accepts 4B5B encoded data symbols scramble or non-scrambled from the PLC-S core at TDAT 4-0 inputs. The 5-bit symbol is clocked into the PDX by the rising edge of LSCLK, serialized, converted to NRZI format and shifted to the outputs. The TX+/TX- pair carries PECL-compatible differential NRZI data to the fiber optic transmitter or to the twisted-pair transceiver interface. The PDX uses LSCLK as the frequency reference to generate the serial link data rate. The external clock source must be crystal controlled and continuous. All of the internal logic of PDX runs on internal clocks that are derived from the external reference source or extracted from the received data. The PDX's clock
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Default Timer and Register Values
The following are the default timer/register values on power-up reset.
Timer/Register MIR (1-0) register TMAX register TVX register and timer TRT timer (bit 20-5) THT timer TNEG register (bit 20-5) TMRS register TREQ0 register TREQ1 register TPRI(1-0) register TSYNC register TMSYNC timer NPADDR 12h & 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1c & 1d 1fh 40h Default Value 00 00 00 00h 03C7h 85h 03C7h
*1
Actual Time Value -NA165.29664 ms 3.4068 ms 165.29664 ms -NA165.29664 ms -NA165.29664 ms
FFFFh*2 03C7h 801Fh 78E0h 0000h
*3
FFFFh 0000h FA97h
*1
-NA-NA3.5456 ms (2xDMAX when ring not operational) -NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-
CMDREG1 CMDREG2 ST1U ST1L ST2U ST2L ST3U ST3L IMSK1U IMSK1L IMSK2U IMSK2L IMSK3U IMSK3L IVR IMR SAID LAIM LAIC LAIL SAGP LAGM LAGC LAGL
00h 01h 00h 01h 02h 03h 61h 62h 04h 05h 06h 07h 63h 64h 65h 66h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh
0000h 0000h 0000h 0007h 4000h 0000h 4000h 0000h FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
SUPERNET 3
67
AMD
Timer/Register MDREG1 MDREG2 MDREG3 STMCHN NPADDR 10h 20h 60h 11h
PRELIMINARY
Default Value 0080h 8000h 0000h xxx0 0000 0000 0000b Actual Time Value -NA-NA-NABits 15, 14, 13 are for the revision number. -NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-NA-
FCNTR LCNTR ECNTR FSCNTR EACB, EARV1, EAS, EAA0, EAA1, EARV2 SACL, SABC RPR1, WPR1, SWPR1 RPR2, WPR2, SWPR2 WPXS, WPXA0, WPXA1 SWPXS, SWPXA0, SWPXA1 RPXS, RPXA0, RPXA1 MARR, MARW WPXSF, RPXSF FRMTHR
41h 42h 43h 44h 22h, 23h, 24h, 25h, 26h, 6bh 28h & 29h 2dh, 2eh, 2fh 68h, 69h, 6ah 30h, 31h, 32h 34h, 35h, 36h 38h, 39h, 3ah 3ch, 3dh 2ah, 2bh 21h
0000h 0000h 0000h 0000h unknown unknown unknown unknown unknown unknown unknown unknown unknown 0000h
Notes: *1 Lower 5 bits are all zero. *2 Lower 5 bits are all one. *3 Only lower 5 bits are valid.
68
SUPERNET 3
PRELIMINARY
AMD
SUPERNET 3 REGISTERS SUPERNET 3 Programmable Registers
Register Mnemonic "cmdreg1" "cmdreg2" "st1u" "st1l" "st2u" "st2l" "imsk1u" "imsk1l" "imsk2u" "imsk2l" "said" "laim" "laic" "lail" "sagp" "lagm" "lagc" "lagl" "mod1" "stmchn" "mir1" "mir0" "tmax" "tvx" "trt" "tht" "tneg" "tmrs" NPADDR7-0 "00" "01" "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0a" "0b" "0c" "0d" "0e" "0f" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" Description Load the Command register 1 instruction Load the Command register 2 instruction Upper 16 bits of status register 1 (Read Only) Lower 16 bits of status register 1 (Read Only) Upper 16 bits of status register 2 (Read Only) Lower 16 bits of status register 2 (Read Only) Upper 16 bits of IMSK register 1 Lower 16 bits of IMSK register 1 Upper 16 bits of IMSK register 2 Lower 16 bits of IMSK register 2 Short Address--individual Long Address, individual (MSW of LAID) Long Address, individual (middle of LAID) Long Address, individual (LSW of LAID) Short Address--group Long Address, group (MSW of LAGP) Long Address, group (middle of LAGP) Long Address, group (LSW of LAGP) Mode Register 1 State Machine register Upper 16 bits--MAC information register (Read Only) Lower 16 bits--MAC information register (Read Only) TMAX register TVX register Upper 16 bits of TRT timer Upper 16 bits of THT timer Upper 16 bits of TNEG register Lower 5 bits of TNEG, TRT, THT timers Bit 14-10--Lower 5 bits of TNEG Bit 9-5--Lower 5 bits of TRT Bit 4-0--Lower THT timer Bit 15 is the Late Count "treq0" "treq1" "pri0" "1a" "1b" "1c" Station's LSW of requested TRT Station's MSW of requested TRT Priority register for ASYNC0
SUPERNET 3
69
AMD
PRELIMINARY
SUPERNET 3 Programmable Registers (continued)
Register Mnemonic "pri1" "pri2" "tsync" "mod2" "frmthr" "eacb" "earv1" "eas" "eaa0" "eaa1" "eaa2" "sacl" "sabc" "wpxsf" "rpxsf" "rpr1" "wpr1" "swpr1" "wpxs" "wpxa0" "wpxa1" "wpxa2" "swpxs" "swpxa0" "swpxa1" "swpxa2" "rpxs" "rpxa0" "rpxa1" "rpxa2" "marr" "marw" "mdru" "mdrl" "tmsync" NPADDR7-0 "1d" "1e" "1f" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2a" "2b" "2d" "2e" "2f" "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3a" "3b" "3c" "3d" "3e" "3f" "40" Description Priority register for ASYNC1 Reserved TSYNC register Mode register 2 Frame threshold register End Address of Claim/Beacon area End Address of receive queue End Address of synchronous queue End Address of asynchronous queue 0 End Address of asynchronous queue 1 Reserved Start Address of Claim frame Start Address of Beacon frame Write pointer for special frames Read pointer for special frames Read Pointer for receive queue Write pointer for receive queue Shadow write pointer for receive queue Write pointer for synchronous queue Write pointer for asynchronous queue 0 Write pointer for synchronous queue 1 Reserved Shadow write pointer for synchronous queue Shadow write pointer for asynchronous queue 0 Shadow write pointer for asynchronous queue 1 Reserved Read pointer for synchronous queue Read pointer for asynchronous queue 0 Read pointer for asynchronous queue 1 Reserved Memory read address register Memory write address register Upper 16 bits of memory data register Lower 16 bits of memory data register TMSYNC register
70
SUPERNET 3
PRELIMINARY
AMD
SUPERNET 3 Programmable Registers (continued)
Register Mnemonic "fcntr" "lcntr" "ecntr" "fscntr" "frselreg" "46" "47" "48" "49" "4a" "4b" "4c" "4d" "4e" "4f" "50l" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5a" "5b" "5c" "5d" "5e" "5f" "mdreg3" "st3u" "st3l" "imsk3u" NPADDR7-0 "41" "42" "43" "44" "45" "46" "47" "48" "49" "4a" "4b" "4c" "4d" "4e" "4f" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5a" "5b" "5c" "5d" "5e" "5f" "60" "61" "62" "63" Mode register 3 Upper 16 bits of status register 3 (Read Only) Lower 16 bits of status register 3 (Read Only) Upper 16 bits of IMSK register 3 Description Frame Counter Lost Counter Error Counter Frame Strip Counter Frame Selection Register
SUPERNET 3
71
AMD
PRELIMINARY
SUPERNET 3 Programmable Registers (continued)
Register Mnemonic "imsk3l" "ivr" "imr" "ilr" "rpr2" "wpr2" "swpr2" "earv2" "unlckdly" "6d" "6e" "lwpr1" "lrwd1" "lwpr2" "lrwd2" "fifoflag" "74" "75" "76" "77" "78" "ltdpa1" "lsa0" "lss" "7c" "7d" "7e" "7f" NPADDR7-0 "64" "65" "66" "67" "68" "69" "6a" "6b" "6c" "6d" "6e" "6f" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7a" "7b" "7c" "7d" "7e" "7f" Last Transmit Descriptor Pointer for Async 1 queue (Hidden) (Hidden) (Hidden) (Hidden) (Hidden) (Hidden) (Hidden) Description Lower 16 bits of IMSK register 3 Interrupt Vector register (Read Only) Interrupt mask register (Hidden) Read pointer for second receive queue Write pointer for second receive queue Shadow write pointer for second receive queue End Address of Receive 2 Queue Auto Unlock Delay Register
"plc_cntrl_a" "plc_cntrl_b" "intr_mask" "xmit_vector" "vector_length" "le_threshold"
"80" "81" "82" "83" "84" "85"
PLC-S control register A PLC-S control register B PLC-S interrupt mask register PLC-S transmit vector register PLC-S vector length register PLC-S link error threshold register
72
SUPERNET 3
PRELIMINARY
AMD
SUPERNET 3 Programmable Registers (continued)
Register Mnemonic "c_min" "tl_min" "tb_min" "t_out" "plc_cntrl_c" "lc_length" "t_scrub" "ns_max" "tpc_load_value" "tne_load_value" "plc_status_a" "plc_status_b" "tpc" "tne" "clk_div" "bist_signature" "rcv_vector" "intr_event" "viol_sym_ctr" "min_idle_ctr" "link_err_ctr" NPADDR7-0 "86" "87" "88" "89" "8a" "8b" "8c" "8d" "8e" "8f" "90" "91" "92" "93" "94" "95" "96" "97" "98" "99" "9a" "9b - af" Description PLC-S Connect state timer register PLC-S line state transmit timer register PLC-S break state timer register PLC-S signalling timeout register PLC_S control register C PLC-S link confidence test timer register PLC-S scrub timer register PLC-S noise timer register PLC-S TPC timer load register (Write Only) PLC-S TNE timer load register (Write Only) PLC-S status register A (Read Only) PLC-S status register B PLC-S TPC (Read Only) PLC-S TNE (Read Only) PLC-S clk_div register (Read Only) PLC-S BIST signature (Read Only) PLC-S PCM receive vector register (Read Only) PLC-S interrupt event register (Read Only) PLC-S violation symbol counter (Read Only) PLC-S minimum idle counter (Read Only) PLC-S link error counter (Read Only) Reserved for future use
"afcmd" "afstat" "afbist" "afcomp2" "afcomp1" "afcomp0" "afmask2" "afmask1" "afmask0" "afpers"
"b0" "b2" "b4" "b6" "b8" "ba" "bc" "be" "c0" "c2" "c3 - cf"
Address Filter Command Register Address Filter Status Register Address Filter BIST Signature Address Filter Comparand 2 Register Address Filter Comparand 1 Register Address Filter Comparand 0 Register Address Filter Mask 2 Register Address Filter Mask 1 Register Address Filter Mask 0 Register Address Filter Personality Register Reserved for future use
SUPERNET 3
73
AMD
PRELIMINARY
SUPERNET 3 Programmable Registers (continued)
Register Mnemonic "orstat" NPADDR7-0 "d2" "d3-df" Description PDX Status Register Reserved for future use
74
SUPERNET 3
PRELIMINARY
AMD
SUPERNET 3 COMMAND REGISTERS SUPERNET 3 Command Registers 1
Instruction Name Software Reset Load MDR from buffer memory with MARR increment Load MDR from buffer memory without MARR increment Idle/Listen Claim/Listen Beacon/Listen Load TVX timer from TVX register Nonrestricted Token Mode Enter Nonrestricted Token Mode Enter Restricted Token Mode Restricted Token Mode Send Unrestricted Token Send Restricted Token Enter Send-Immediate Mode Exit Send- Immediate Mode Clear Synchronous Queue Lock Clear Asynchronous Queue 0 Lock Clear Asynchronous Queue 1 Lock Reserved Clear Receive Queue 1 Lock Clear Receive Queue 2 Lock Tristate X Bus (in SAS only) Drive X Bus Clear All Queue Locks Code 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 11h 12h 14h 18h 20h 21h 22h 23h 3Fh IRMEMWI IRMEMWO Mnemonic
SUPERNET 3 Command Registers 2
Instruction Name Reserved Reserved Reserved Reserved Abort Current Transmit Activity Reset Transmit Queues Set Tag Bit Reserved Transmit Command Code 01h 02h 04h 08h 10h 20h 30h 40h 50h Mnemonic
SUPERNET 3
75
AMD
PRELIMINARY The AFSTAT register, bit 7-5, provides a three-bit binary value that indicates the revision number of the Address Filter block. The revision I.D. shall be `111'. The ORSTAT register, bit 2-0, provides a three-bit binary value that indicates the revision number of the PDX block. The revision I.D. shall be `111'. All other bits of ORSTAT register are reserved.
Revision I.D.
The bits 13, 14, 15 of the State Machine Register provides a three-bit binary value that indicates the revision number of the SUPERNET 3. The revision I.D. shall be `111' for the first revision. The PLC_STATUS_A register, bit 15-11, provides a five-bit binary value that indicates the revision number of the PLC-S block within the SUPERNET 3. The revision I.D. shall be `01111'.
76
SUPERNET 3
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature . . . . . . . . . . . . . . 0C to +70C Supply Voltage Referenced to VSS . . . . . . . . . . . . . . -0.3 V to +6.0 V DC Voltage applied to any Pin Referenced to VSS . . . . . . . -0.5 V to VCC + 0.5 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGES
Temperature, TA . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltages, VCC . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter Symbol VIL VIH VIL VIH IIL IIH IOZ VOH VOL VOL VOH IOL IOL IOH IOZ IIX ICC Parameter Description Input Low Voltage Input High Voltage Input Low Voltage (Note1) Input High Voltage (Note 1) Input Low Current (Note 9) Input High Current (Note 9) Output Leakage Current (Note 10) Output High Voltage (Note 2) Output Low Voltage (Note 2) Output Low Voltage Output High Voltage (Note 4) Output Low Current (Note 5) Output Low Current (Note 6) Output High Current Output Leakage Current (Note 7) Input Leakage Current (Note 8) Power Supply Current 0.4 V < VOUT < VCC 0 V < VIN < VCC VCC = Maximum -10 -10 VCC = Maximum, VIN = 0.5 V VCC = Maximum, VIN = 2.7 V 0.4 V < VOUT < VCC PECL Load (Note 3) PECL Load (Note 3) IOL = Maximum IOH = -IOL/2 2.4 8.0 4.0 -IOL/2 10 10 400 -10 VCC-1.025 VCC-1.81 2.0 VCC-1.81 VCC-1.475 VCC-1.165 VCC-0.88 -200 -100 10 VCC-0.6 VCC-1.62 0.4 Test Conditions Min Max 0.8 Unit V V V V A A A V V V V mA mA mA A A mA
Notes: 1. Applies to PECL inputs only RX+ ,RX-, SDI+,SDI-. 2. Applies to PECL outputs only TX+,TX-. 3. Tested for VCC = Minimum, shown limits are specified over entire VCC operating range. 4. VOH does not apply to open-drain pins READY, MINTR[4:1]. 5. An IOL value of 8.0 mA applies to the following signals: ADDR[15:0], WR, RD, BD[31:0], BDP[3:0], BDTAG, CSO, MINTR[4:1], and READY. 6. An IOL value of 4.0 mA applies to all signals except those listed in Note 5. 7. IOZ applies to all three-state output pins and bidirectional pins. 8. IIX applies to all non-PECL input-only pins. 9. IIL, IIH applies to all TTL pins. 10. IOZ applies to TDO.
SUPERNET 3
77
AMD
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply
OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010
78
SUPERNET 3
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clocks
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Parameter Symbol tPER tPWH tPWL tPER tPWH tPWL tPER tPWH tPWL tPER tPWH tPWL tSK tSK tSK Parameter Description LSCLK Period LSCLK High Pulse Width LSCLK Low Pulse Width BCLK Period BCLK High Pulse Width BCLK Low Pulse Width BMCLK Period (BMCLK tied to BCLK) BMCLK High Pulse Width (BMCLK tied to BCLK) BMCLK Low Pulse Width (BMCLK tied to BCLK) BMCLK Period (BMCLK tied to LSCLK) BMCLK High Pulse Width (BMCLK tied to LSCLK) BMCLK Low Pulse Width (BMCLK tied to LSCLK) BMCLK to BCLK Skew (BMCLK tied to BCLK) BMCLK to LSCLK Skew (BMCLK tied to LSCLK) LSCLK to BCLK Skew Min 40 18 18 80 35 35 80 35 35 40 18 18 0 0 0 Max 40 22 22 80 45 45 80 45 45 40 22 22 0 0 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SWITCHING WAVEFORMS
1 LSCLK
2
3
15 4 BCLK 6 5
13 7 BMCLK (BMCLK tied to BCLK) 14 10 BMCLK (BMCLK tied to LSCLK)
8
9
12
11
19574A-29
Figure 28. Clock Timings
SUPERNET 3
79
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges NP
No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Parameter Symbol tS tEN tPD tS tPD tZ tH tINV tZ tPWH tS tH tS tH tS tH tZ tEN tPD tINV tS tH tPD tZ tPD tZ tPWL tS tH tPD tPD tPD Parameter Description R/W and NPADDR[7:0] Setup Time to DS (CSI) Low DS(CSI) Low to NPDATA[15:0] Enabled (Asynchronous Read) DS(CSI) Low to NPDATA[15:0] Valid (Asynchronous Read) NPDATA[15:0] Setup Time before READY Low (Asynchronous Read) DS (CSI) Low to READY Low DS (CSI) High to READY Deasserted R/W and NPADDR[7:0] Hold Time from DS (CSI) High NPDATA[15:0] Invalid from DS (CSI) High (Asynchronous Read) DS(CSI) High to NPDATA[15:0] Deasserted DS High to DS Low (Asynchronous Read/Write Recovery Time) NPDATA[15:0] Setup Time to DS (CSI) Low (Asynchronous Write) NPDATA[15:0] Hold Time from DS (CSI) High (Asynchronous Write) CSI Setup Time to BCLK CSI Hold Time to BCLK R/W and NPADDR[7:0] Setup Time to BCLK R/W and NPADDR[7:0] Hold Time to BCLK BCLK to NPDATA[15:0] Deasserted BCLK to NPDATA[15:0] Enabled BCLK to NPDATA[15:0] Valid BCLK to NPDATA[15:0] Invalid NPDATA[15:0] Setup Time to BCLK NPDATA[15:0] Hold Time to BCLK BCLK LOW to READY LOW BCLK HIGH to READY Deasserted BCLK to MINTR[4:1] Valid BCLK to MINTR[4:1] Deasserted RST Pulse Width Low NPMEMREQ Setup Time to BMCLK NPMEMREQ Hold Time to BMCLK BMCLK to NPMEMACK High BMCLK to NPMEMACK Low BMCLK High to CSO, RD, WR, ADDR15-0 Disabled (20*tPER4) 15 10 20 20 30 2 30 20 25 35 25 25 2 30 100 -60 0 10 10 10 10 30 0 5 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 310 35 Min 0 0 275 ns ns ns ns ns Max Unit ns
80
SUPERNET 3
PRELIMINARY
AMD
SWITCHING WAVEFORMS
CSI
35 DS
26
32
26
R/W
NPADDR 34 28 33 NPDATA 27 29 READY Note 1 30 31 Open Drain 27
Note 2
Notes: 1. 26, 27, 28, and 30 are measured from CSI or DS whichever goes LOW last. 2. 31, 33, 34, and 32 are measured from CSI or DS whichever goes HIGH first.
19574A-30
Figure 29. NP Asynchronous Read
SUPERNET 3
81
AMD
PRELIMINARY
SWITCHING WAVEFORMS
CSI
35 DS
26 R/W
32
26
NPADDR
36
37 27
NPDATA
READY Note 1 30
31 Open Drain
Note 2
Notes: 1. 26, 36, and 30 are measured from CSI or DS whichever goes LOW last. 2. 31, 32, and 37 are measured from CSI or DS whichever goes HIGH first.
19574A-31
Figure 30. NP Asynchronous Write
82
SUPERNET 3
PRELIMINARY
AMD
SWITCHING WAVEFORMS
4 BCLK 38 CSI 6 38 5
39 R/W
39
41
40
NPADDR
40
44
41
42
NPDATA
42 43
45 46 42
47
49 READY 48 49 Open Drain 48
19574A-32
Open Drain
Note: 1. DS is ignored in Synchronous mode and should be inactive (High) during all Synchronous accesses.
Figure 31. NP Synchronous Read and Write Except MDR Accesses
SUPERNET 3
83
AMD
PRELIMINARY
4 BCLK 38 CSI
5
6
38
39 R/W
39
41
40
NPADDR
40
44
41
42
NPDATA
42 43
45 46 42
47
49 READY 48 49 Open Drain 48
19574A-33
Open Drain
Notes: 1. DS is ignored in Synchronous mode and should be inactive (High) during all Synchronous accesses. 2. Read and Write Cycles could extend beyond two clock cycles.
Figure 32. NP Synchronous Read and Write MDR Accesses
84
SUPERNET 3
PRELIMINARY
AMD
SWITCHING WAVEFORMS
4 5
BMCLK 53 6 54
NPMEMREQ 55
56
NPMEMACK 57 CSO
RD
57
WR
57
57 ADDR
19574A-34
Figure 33. NP DMA Signals
SUPERNET 3
85
AMD
PRELIMINARY
SWITCHING WAVEFORMS
4 5
BMCLK 6 MINTR[4:1] 50 51
Open Drain
52
RST
19574A-35
Figure 34. NP Miscellaneous Signals
86
SUPERNET 3
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Host Interface & Buffer Memory
No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 121 122 123 tPD tPD tPD tPD tS tPD tPD tPD tS tPD tPD tPD Parameter Symbol tS tH tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD tS tH Parameter Description HSREQ2-0 Setup Time to BMCLK High HSREQ2-0 Hold Time to BMCLK High BMCLK High to HSACK High BMCLK High to HSACK Low BMCLK High to RDATA High BMCLK High to RDATA Low BMCLK High to QCNTRL2-0 Valid QCNTRL2-0 Invalid from BMCLK High BMCLK High to ADDR 15-0 Enabled BMCLK High to ADDR 15-0 Valid BMCLK High to CSO Low BMCLK Low to RD Low BD 31:0, BDP 3:0, BDTAG Setup Time to RD High BD 31:0, BDP 3:0, BDTAG Hold Time from RD High Reserved CSO Invalid from RD or WR High ADDR 15:0 Invalid from RD or WR High BMCLK Low to WR Low ADDR 15:0 Valid to WR Low Setup Time BMCLK Low to BD 31:0, BDP 3:0, BDTAG Enabled BMCLK Low to BD 31:0, BDP 3:0, BDTAG Valid BD 31:0, BDP 3:0, BDTAG Valid before WR High Reserved BD 31:0, BDP 3:0, BDTAG Invalid from WR High BMCLK High to BD 31:0, BDP 3:0, BDTAG Disabled Read Pulse Width Write Pulse Width ADDR 15:0 Valid to RD Low Setup Time 38 37 7 14 0 30 43 15 0 0 26 0 4 18 10 0 5 0 27 26 22 Min 15 5 25 25 25 25 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SUPERNET 3
87
AMD
PRELIMINARY
SWITCHING WAVEFORMS
BMCLK 76
77
HSREQ
78
79
HSACK 84
92
ADDR15-0 85 CSO 86
123
91
RD or WR 87 93
122 121
RDATA
80
81
QCTRL2-0 82 83
19574A-36
Figure 35. Host Interface Signal Timings
88
SUPERNET 3
PRELIMINARY
AMD
SWITCHING WAVEFORMS
BMCLK 84 92 ADDR15-0 91
85 CSO 86
RD 87 BD31-0, BDP3-0, BDTAG 88
121
89
19574A-37
Figure 36. Buffer Memory Read Cycle Timings
BMCLK 84 92 ADDR15-0
85 CSO 86 94 WR
91
93 BD31-0, BDP3-0, BDTAG
122 100
95 96 97
99
19574A-38
Figure 37. Buffer Memory Write Cycle Timings SUPERNET 3 89
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges External PHY Interface Timing
No. 126 127 130 131 Parameter Symbol tPD tPD tS tH Parameter Description BCLK High to X-Bus (X0-7, XCU, XCL) Valid X-Bus (X0-7, XCU, XCL) Invalid from BCLK High R0-7, RCU, RCL Setup Time to LSCLK Low R0-7, RCU, RCL Hold Time to LSCLK Low 6 10 5 Min Max 35 Unit ns ns ns ns
SWITCHING WAVEFORMS
LSCLK
130 131
R-Bus (R0-R7, RCU, RCL)
BCLK
127 126
X-Bus (X0-X7, XCU, XCL)
19574A-39
Figure 38. PHY Interface Timings
90
SUPERNET 3
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges MAC Miscellaneous Signal Timing
No. 140 141 142 143 144 145 Parameter Symbol tS tH tPD tPD tS tH Parameter Description FLXI/XMTINH Setup Time to BCLK High FLXI/XMTINH Hold Time from BCLK High BCLK High to RS5-0, XS3-0 Valid RS5-0, XS3-0 Invalid from BCLK High XSAMAT, XDAMAT, XSA_XACT, XDA_XACT Setup Time to BCLK High XSAMAT, XDAMAT, XSA_XACT, XDA_XACT Hold Time from BCLK High 5 20 5 Min 30 5 35 Max Unit ns ns ns ns ns ns
SWITCHING WAVEFORMS
BCLK
140 141
FLXI
142
143
RS5-0 XS3-0
XSAMAT XDAMAT XSA_XACT XDA_XACT
144
145
19574A-40
Figure 39. MAC Miscellaneous Signal Timings
SUPERNET 3
91
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges External CAM Interface Timing
No. 156 157 Parameter Symbol tPD tPD Parameter Description BCLK High to RXAFU3-0, RXAFL3-0, RXAFCU, RXAFCL Valid RXAFU3-0, RXAFL3-0, RXAFCU, RXAFCL Invalid from BCLK High 0 Min Max 25 Unit ns ns
SWITCHING WAVEFORMS
BCLK
156
157
RXAF Bus (RXAFU0-RXAFU3, RXAFL0-RXAFL3, RXAFCU, RXAFCL)
19574A-41
Figure 40. External CAM Interface Timings
92
SUPERNET 3
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PHY Miscellaneous Signal Timing
No. 200 201 210 211 Parameter Symbol tPD tPD tS tH Parameter Description FOTOFF, LSR 2-0, ULSB, EBFERR Valid from BCLK High FOTOFF, LSR 2-0, ULSB, EBFERR Invalid from BCLK High ENCOFF Setup Time to BCLK High ENCOFF Hold Time from BCLK High 0 15 10 Min Max 25 Unit ns ns ns ns
SWITCHING WAVEFORMS
BCLK
201
FOTOFF LSR 2-0, ULSB, EBFERR
210 200
ENCOFF
211 19574A-42
Figure 41. PHY Miscellaneous Signal Timings
SUPERNET 3
93
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Test Interface Signal Timing
No. 226 227 228 229 230 231 232 Parameter Symbol tPER tPWH tPWL tS tH tINV tPD Parameter Description TCLK Period TCLK Pulse Width High TCLK Pulse Width Low TDI, TMS, TRST Setup Time to TCLK High TDI, TMS, TRST Hold Time from TCLK High TDO Invalid from TCLK Low TDO Valid from TCLK Low Min 80 45% 45% 25 6 0 30 Max 1000 55% 55% ns ns ns ns Unit ns
SWITCHING WAVEFORMS
226 227 228
TCLK
231
TDO
229 232
TDI, TMS TRST
230 19574A-43
Figure 42. TEST Interface Signal Timings
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SUPERNET 3
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PMD Interface Signal Timing
No. 250 251 252 253 254 Parameter Symbol tR| tF| tSK| tS tH Parameter Description TX+, TX- Rise Time TX+, TX- Fall Time TX+ to TX- Skew SDI Setup Time to LSCLK High SDI Hold Time from LSCLK High Test Conditions PECL Load PECL Load PECL Load 7 5 Min 0.3 0.3 Max 3 3 200 Unit ns ns ps ns ns
Note: |: Not included in the production test.
VOH
250 251
TX+, TX-
VOL
80% 20%
VOL
TX+
252
TX-
1
LSCLK
253 254
SDI
19574A-44
Figure 43. PMD Interface Signal Timings
SUPERNET 3
95
AMD
PRELIMINARY
REFERENCES PHY Device
1] AMD Am79C864A in The SUPERNET 2 Family for FDDI, Publication no. 15502, Rev. C, Physical Layer Controller with Scrambler/ Descrambler (PLC-S). 2] ANSI X3.148-1988, FDDI Physical Layer Specification. 3] ANSI X3T9 SMT Ver. 7.2, Station Management Specification.
MAC Device
1] AMD Am79C830A Formac Plus datasheet in The SUPERNET 2 Family for FDDI, Publication no. 15502, Rev. C. 2] ANSI X3.139-1987, FDDI Media Access Control Specification.
Testability
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990 (Approved Feb. 15, 1990)
96
SUPERNET 3
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AMD
PHYSICAL DIMENSIONS* PQR208, Trimmed and Formed 208-Pin Plastic Quad Flat Pack (measured in millimeters)
30.40 30.80
Pin 208
25.50 REF
27.90 28.10
Pin 156
Pin 1 I.D.
25.50 REF 27.90 28.10 30.40 30.80
Pin 52 Pin 104
3.20 3.60 0.25 Min
0.50 BASIC
3.95 MAX
SEATING PLANE
16-038-PQR-2 PQR208 DA92 7-20-94 ae
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Trademarks Copyright (c) 1995 Advanced Micro Devices, Inc. All rights reserved. SUPERNET, AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
SUPERNET 3
97

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